Design Research On The Digital Background Calibration In Pipelined ADC

With the rapid development of video processing, audio processing and wireless communication industry, high speed and high resolution of the analog to digital converter has been widely used. Especially the pipelined ADC with its high resolution and high speed gets the favor. Along with the continuous development of digital chips according to Moore’s law, the improvement of the performance of pipelined ADC largely depends on the improvement of digital circuit. Such as, the comparator offset voltage error, amplifier gain error and capacitor mismatch error can be corrected through the digital calibration circuit.This thesis mainly analyse sub-ADC’s comparator offset voltage error, Sub-DAC’s capacitance mismatch error and amplifier’s gain error of pipelined ADC in detail as well as the error sources and the influence on the output result of the conversion circuit. The above three kinds of errors affect the performance of the system and their influence can be reduced gradually with the increase of stages, therefor the first stage circuit’s structure is particularly important.Differring from the 1.5bit/stage, this paper studies and resolves the structure of the 2.5bit/stage, this structure adopted is not only available to make pipelined ADC reach high resoulation but also greately reduce the complexity of circuit and shorten design period and also help save cost. The 2.5bit/stage ADC circuit can stand the errors within 1/8Vref by digital calibration circuit so that the performance of the ADC is not impacted.Simulink of Matlab is applied to analyse the 12 bit ideal pipelined ADC. The error model of internal gain error between stages is 2% and capacitor mismatch error is 0.1%. It is can be seen that the effect of capacitor mismatch error on the performance of pipeline ADC is prominent and even is the key factors that determine the performance of pipeline ADC. Based on the importance of the capacitor mismatch error, this paper adopts a new correction algorithm for capacitor mismatch error.Based on the analysis and research of pipelined ADC with multi-bits DAC capacitance component mismatch, this thesis proposes a digital background calibration technique,which does’ t need to interrupt the normal modules’ conversion process while recoding the Flash ADC digital output per level to make the DAC be reshaped as white noise to enhance the SFDR performance; then the white noise is cancelled from the signal by adopting DNC technique. Simulink used to model the behavior of this calibration technique and simulation results show that the ideal SNDR, SFDR and effective precision are repectively 72 d B, 86 d B and 12 bit when the input signal is 5d B&6.25 MHz and the sampling frequency is 100 MHz. However, the actual SNDR, SFDR and effective bit number are respectively 59 d B, 68 d B and about 10 bit due to the existence of the capacitance mismatch of DAC component, which cannot meet adequately necessary performance requirements of the actual application. DEM technology and DNC digital correction technology are applied to the first three stages circuits of pipelined ADC. The simulation indicates that the SNDR, SFDR and effective resoulation are improved to respectively 71 d B, 85.9d B and 12 bit which meets the performance requirements for practical applications. The design analysis results show that the discussed digital background correction technique can greatly improve pipelined ADC’s SNDR and SFDR, in additon to relaxing the precision requirement of the devices of analog circuits in pipelined ADC and obviously shortening the design period of the circuit design as well as helping reduce the power consumption and area of the analog circuit.