Research And Implementation Of The16-bit100MSPS Pipelined ADC Digital Self-correction Technology

With the fast development of digital communications technology and signalprocessing system, people have strictly requirements of the analog-to-digital converter(ADC). High-speed, high-precision, low-power and low-cost digital-to-analogconverters become the pursuit of goals. However, the traditional ADC is difficult toachieve the speed and accuracy compatible. Urgent market demand, the development ofthe pipelined ADC becomes irresistible and it will be the mainstream ADC of ICTindustry.The development of pipelined ADC provides people a good market prospect, at thesame time the accuracy increasing requirements bring us some challenges. Due to themetal capacitance matching accuracy can only reach about10, when the pipelined ADCaccuracy requirements more than10, the capacitor mismatch error will become animportant source of pipelined ADC nonlinear. To be able to achieve16-bit100MSPSpipelined ADC, calibration technology must be used in the design process to eliminatethe effect of capacitor mismatch error to increase a pipelined ADC accuracy. There aretwo ways to correct the error in the design process, the analog circuit calibrationtechnology and digital self-calibration techniques. As CMOS technology feature sizescontinue to shrink, the design of analog circuits become more complex, and therefore, inorder to better combination of process development, the design uses digitalself-calibration technology on the calibration of the16-bit100MSPS pipelined ADC.Starting with all levels of structure and working principle of the pipelined ADC,Then gradually analysis the error and the effect of error performance to pipelined ADC.In the error analysis process, I focus on analysis the capacitor mismatch error. Based onthe theoretical derivation of the capacitance mismatch error, we can implement thetechnology of digital self-calibration. The concrete realization of the process: achievedthe behavioral simulation of digital self-calibration algorithm with Matlab software.Accomplished the description of self-calibration algorithm with hardware language andgenerated fully functional Verilog code, then finished the function simulation; aftergetting correct functional simulation, we combined Physical Compiler software (Design Compiler) with technology library file to get a circuit netlist. Finally using the circuitnetlist to generate layout by automatic placement and routing tools. Then we can get thelayout file of digital self-calibration circuit directly.This design achieves16-bit100MSPS pipelined ADC digital self-calibrationsystem based on SMIC0.18μm CMOS process and simulates the function. Finally, thelayout area is1mm~2.