14-bit 320MS/s Pipelined-SAR ADC IP Design

The purpose of this paper is to design a 14-bit resolution,320MS/s sampling rate and low power ADC IP.The commonly used ADC structures include pipelined ADC,successive approximation(SAR)ADC,flash ADC,and ?-? ADC.In the field of high performance and low power ADC,SAR ADC is widely used because of its characteristics of lower power consumption,simple structure and easy to integrate.On the other hand,the pipelined ADC is made up of several level circuits,and each level completes the conversion in one clock cycle,which is equivalent to one clock cycle to complete a conversion from the whole system,so pipelined ADC can achieve high speed and high accuracy through relatively high power consumption.These two structures of ADC will encounter different technological bottlenecks with the improvement of performance.With the increase of sampling rate,the aperture error redundancy of pipelined ADC decreases rapidly,resulting in the decline of performance under the situation of high frequency input.With the increase of resolution,the stage resolution of pipelined ADC increases,and the power consumption of sub flash ADC increases exponentially with resolution.The demand of low noise and high bandwidth of comparator greatly increases when SAR ADC achieves high accuracy and high speed.In order to overcome these problems and achieve high performance,this paper uses Pipelined-SAR ADC to achieve the design requirements of high performance and low power consumption.Using the Pipelined-SAR structure is equivalent to use SAR ADC as sub ADC in the pipeline structure,that is,the problem of aperture error is eliminated,and the flash ADC is replaced,which means the power consumption is reduced.Add the residual amplifier in the high-precision SAR ADC,reducing the demand of low power in both two level SAR ADC comparator.For SAR ADC,though the offset of comparator will cause the decline of SNR,but the influence are less.However,in Pipelined-SAR ADC,the top plate of first stage SAR ADC capacitor array is connected to both the input of comparator and the input of residual amplifier,the mismatch of modules caused by offset greatly affects the performance of ADC.Considering that the structure of the dynamic pre-amplifier in the comparator can be used as a residual amplifier,the pre-amplifier in this work is multiplexed,it is multiply used as part of the comparator and inter-stage amplifier,which eliminating the influence of mismatch and alleviating the parasitic of key nodes.The gain calibration is used for gain instability of dynamic amplifier.Meanwhile,a background calibration method based on Dither injection is added for extreme corner or other circumstance.This design is fabricated in tsmc 28 nm CMOS technology,the design of schematic and layout are completed,as well as comprehensive simulation.The core area of ADC is 100?m×70?m.The sampling rate is 320MS/s.In schematic simulation results,at low input frequency ENOB=14.09,at Nyquist input frequency ENOB=13.86.In layout simulation results,at low input frequency ENOB=13.90,at Nyquist input frequency ENOB=13.13,taking into account the transient noise ENOB=11.73,SNDR=72.35.The power consumption of ADC is 2.87 mW and the FOM is 2.64fJ/con-step.These simulation results indicate that the design objective is basically achieved.