Reserch And Implementation Of Pipeline ADC Digital Calibration Technology

As a bridge between analog signal and digital signal,ADC has become an important part of modern electronic system.Among the many implementation architectures of ADC,pipeline architecture has good potential in achieving ultra-high speed and high precision.However,the existence of non ideal factors such as noise,misalignment and mismatch limit the improvement of the overall performance of pipeline ADC.Therefore,calibration technology must be introduced to calibrate the non ideal factors to ensure the high performance of pipelined ADC.The research status of pipelined ADC and its calibration technology is comprehensively investigated,and the advantages of pipeline structure and the necessity of calibration technology in its high performance implementation are clarified.According to the basic principle of pipelined ADC,the behavioral modeling of 18-bit 20MS/s pipelined ADC is completed based on verilog-A.This dissertaion analyzes the errors caused by non ideal factors in pipelined ADC,and introduces the existing calibration technology aiming at these error sources,which set a good foundation for the design of digital calibration algorithm of pipelined ADC.For capacitor mismatch error,a digital calibration algorithm based on the height of jump point is designed to eliminate the influence of process deviation on the accuracy of pipelined ADC;For gain error,a digital calibration algorithm based on programmable feedback capacitor array is designed to reduce the difficulty of high gain operational amplifier design;For sampling time mismatch error,a digital calibration algorithm based on variable delay line is designed to make up for the defect of SHA-less pipelined ADC in high frequency applications.In this dissertaion,the digital calibration algorithms are designed based on Verilog and applied to an 18-bit 20MS/s Pipeline ADC.The simulation results show that when there is a capacitance mismatch error of 1‰,the ENOB increases from 13.41-bit to 16.83-bit,and the SFDR increases from 88.44 dB to 106.17 dB;When there is 5‰ gain error,the ENOB increases from 12.51-bit to 17.84-bit,and the SFDR increases from 89.23 dB to 130.3dB;When there is a100 ps sampling time mismatch error,the ENOB increases from 13.25-bit to 17.86-bit,and the SFDR increases from 93.49 dB to 130.23 dB.Finally,the layout is designed based on 0.18 ?m CMOS process,and the formal verification and timing analysis of digital calibration algorithm are completed.