Correction Algorithms Suitable For High-precision Pipelined Adc

Pipeline ADC (Analog-to-Digital Converter) is widely used in wide-band communication systems and video imaging, due to its advantages of high speed, high resolution, low power consumptions and low die areas. However, its linearity is limited by opa's finite open-loop gain, capacitor mismatch, and other non-ideal factors. Calibration is one of the important research fields of ADC, since it can effectively reduce effects of errors and improve ADC's resolution and dynamic range, under the modern IC design and manufacture level.Backend calibrations on gain errors and capacitor mismatch in pipeline ADC are studied in this paper. A digital backend gain calibration method for multi-bit stages is proposed. Using a reformative redundant stage, gain errors are measured by PR (pseudo-random) signal being injected at sub-DAC output and compensated in background according to the estimated value. Simulations are performed for a 12-bit pipeline ADC. Assumed the relative gain error of 3-bit first stage is±2% respectively, with calibration simulations show an improvement of 35 dB in SFDR, 16 dB in SNDR,0.16 LSB of INL under both conditions, 0.13 LSB and 0.14 LSB of DNL respectively. Based on SMIC 0.18μm Si-CMOS process model, the key calibration circuits are designed and simulated using HSPICE, and the results are the same to that of Matlab. Analyses show that the proposed method can calibrate positive or negative gain errors in multi-bit stage without reducing the conversion range or increasing extra comparators.A digital backend calibration method based on PR signal is used to calibrate capacitor mismatch in 1.5-bit pipeline stage. Using modified 1.5-bit redundant stage, injecting PR signal at sub-DAC output to get residue voltages, while the transfer curves dithering with PR signal and input signal range, then correlating residue voltages with the same PR sequence to obtain calibrated coefficients, which are used to compensate the mismatch errors. Simulations are performed for a 12-bit pipeline ADC with 99.9% full-scale sine-wave. Assumed the error of first stage is±0.25% respectively, with calibration simulations show an improvement of 16 dB and 19 dB in SFDR respectively. Based on SMIC 0.18μm Si-CMOS process model, the key calibration circuits are designed and simulated using HSPICE, and the results are the same to that of Matlab. Analyses show that this backend calibration for capacitor mismatch is effective; in addition, it can shorten the calibration time by allowing the injection of a large dither without sacrificing the signal range.