Research And Implementation On Digital Calibration Of A Low Voltage High Speed Pipelined ADC

Modern society has run into a stage in which all kinds of information represented by digital signals rises explosively. The applications of analog to digital converters(ADCs) which convert the continuous analog signals to digital signals become wider and wider. Meanwhile, the complexity of various applications demands for better and better ADCs. As the pipelined ADCs can achieve a mid-high speed and mid-high resolution, they become the most widely used ADCs in mid-high speed applications and they are academic researched most by IC scholars and engineers. However, the disadvantage of large power consumption in pipelined ADCs and the most power hungry block “Sample and Hold”(SHA) make the design of SHA-less pipelined ADCs more and more popular in high speed low power applications.Firstly, the basic operation principles were introduced and a mathematic model of pipelined ADC was built in the thesis. After thorough analysis of various error causes and how they affected the system, a SHA-less 10 bits 500 MSPS pipelined ADC model was built using the tool of Matlab. To reduce the capacitor mismatch error and the gain error, a calibration method was offered which combined foreground calibration and background calibration technique and the function of calibration was testified. The results of simulation showed that the calibration method could promote the dynamic range and noise performance by adding 3 bits to the effective resolution.Secondly, the calibration method which was already testified was translated to digital circuit of RTL level which could be synthesized using the hardware language VHDL. The VHDL based code was simulated using EDA tool Modelsim. The simulation results showed that all the errors to be calibrated had a process of calibrating and the final gain and capacitor mismatch were in the logical range.Finally, according to the design flow of digital integrated circuits, the RTL level HDL code was translated to physically implemented digital layout based on standard 0.13 μm CMOS foundry using EDA tools Design Complier and Encounter. The final digital layout had a size of 800μm * 600μm.