Research And Design Of Key Technologies Of SerDes Receiver

With the rapid development of network technology and hardware manufacturing technology,the amount of data transferred between systems is increasing rapidly.As a result,the data rate of the transmission interface becomes the key factor limiting system performance improvement.Due to the weak anti-interference ability,parallel transmission is prone to crosstalk,clock skew and so on,which makes it difficult to improve the data transmission rate.However,serial transmission can effectively solve these problems to achieve higher transmission rate.In addition,serial transmission has the advantages of few ports,low power consumption and so on.Therefore,more and more attention has been paid to serial link technology(SerDes),which has gradually become the mainstream technology of data transmission.In this paper,based on the research of the SerDes system,the loss of signal detection circuit and the clock and data recovery circuit of the SerDes receiver are designed based on the SMIC 0.13 ?m CMOS Technology.Moreover,a simulation method of jitter tolerance is proposed.The loss of signal detection circuit filter out severely distorted signals and the noise that is coupled to the input,by measuring differential amplitude of the input signal.In this paper,the threshold voltage of the loss of signal detection circuit can follow the change of the common mode voltage of the input signal.This can make the detection result is not affected by the common mode voltage of the input signal.The clock and data recovery circuit is designed based on phase interpolation.The circuit design of phase tracking loop is presented in this paper,which includes data sampling circuit,phase detection circuit,voter,interpolation control circuit and phase interpolation circuit.Among them,the phase detection circuit is designed by using the Bang-Bang half rate phase detector.As a result,sampling clock frequency does not exceed data transfer rate and the data transmission rate is improved.The method of phase interpolation is to divide the full cycle into 8 phases,and then adjust the clock phase in the phase interval of the clock.This method reduces the interpolation step,and is helpful to accurately adjust the clock phase.In this paper,a method to simulate the jitter tolerance is proposed,which is based on the VerilogA language to generate the pseudo random data with jitter as the test signal,and to judge whether the simulated output signal is wrong by Python script.This method verifies the jitter tolerance in the chip design stage,which effectively reduces the risk of tape-out.The jitter tolerance simulation results show that the jitter tolerance is 0.61 UI when the jitter frequency is between 0.1MHz and 10 MHz.After the SerDes circuit design is completed,the layout of the chip is designed,and then the chip is taped out,then the SerDse chip after tape-out were tested.The SerDes chip area is 2363×2422?m.The test results show that the chip works correctly and the data transfer rate can reach 2.5Gbps.