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Keyword [jitter tolerance]
Result: 1 - 6 | Page: 1 of 1
1.
The Design And Verification Of The Clock Data Recovery Circuit In SerDes
2.
Research And Design Of Key Technologies Of SerDes Receiver
3.
A 2-5 Gbps fully differential 3X oversampling CDR for high-speed serial data link
4.
A CDR with a digital threshold decision technique and a cyclic reference injected DLL frequency multiplier with a period error compensation loop
5.
Research And Design Of Low Jitter And High Speed Clock And Data Recovery Circuit
6.
Design And Implementation Of SerDes Interface Test Modules
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