Design Of PI Based Clock And Data Recovery Circuit For Serdes

With the development of network and large data, people’s demand for information transmission has made a sharp growth. The traditional parallel interface has seen increasing restriction, and high-speed serial interface technology gradually become the mainstream way of communication. The common serial communication protocols include UART, USB, IEEE1394, etc. The1394interface with its characteristic of multi channel and high rate is widely used in system bus and video transmission. The transmission standard of1394interface is developed in1995by IEEE (Institute of electrical and Electronics Engineers). Its transmission peak can reach400MB/S, while supporting100MB/S and200MB/S transmission rate. In2001, IEEE enacts1394B protocol as a new standard of1394interface. Its transmission speed can reach800MB/S, and the number can be improved to32GB/S in plastic optical fiber.This thesis first introduces the function of serial links, describing the relationship between CDR (Clock and Data Recovery) and other modules in Serdes. Secondly, it elaborates the concept of jitter and data coding in clock and data recovery circuit, analyzing the design index. Through comparison and analysis of different structure of CDR circuit, phase interpolation type CDR is selected as the circuit structure of this design and some core modules are determined such as Alexander phase detector and two order digital loop filter. Then this thesis completes circuit design and simulation of each module, including sampling module, string module, loop filter, phase interpolation circuit and clock selection circuit. Finally, the whole CDR circuit transient simulation is made to observe the eye diagram of dithering data and calculate the locking time of recovered clock, verifying whether it meets the design index of1394B.The phase interpolation based clock and data recovery circuit for Serdes, designed in this paper, follows the1394B protocol, supporting800MHz,400MHz and100MHz data transmission frequency, using four phase clock from external phase-locked loop. The phase interpolation circuit is controlled by a64-bit parallel computing and the accuracy of recovery clock isπ/32. The schematic and layout design is completed with Cadence EDA tools and the simulation with Spectre. Through the simulation, the recovery clock jitter and locking time can satisfy the index of Serdes1394B, and the clock can achieve recovery function to input signal.