| With the rapid development of Ser Des(Serializer/Deserializer)technology,wired communication equipment has higher requirements for the speed and quality of Ser Des data transmission.The main factors affecting the quality of high-speed Ser Des data transmission are the non-ideal characteristics of channel and package.CDR(Clock and Data Recovery)isμsed to recover the clock and data with less jitter from the input data containing jitter information.It is a key module to determine the quality of received data in the communication system.In addition,the rise of 5G,Internet of things,optical communication,and other fields makes the speed,power consumption and cost of CDR become the key factors in the competitiveness of interface chip products.Therefore,the research of high-speed,low power consumption,low jitter,no reference source clock data recovery circuit has important theoretical and engineering application value.Based on 22 nm Global Foundries FDSOI(Fully Deployed Silicon-on-Insulator)technology,a high-speed,low jitter,and no reference source single loop clock data recovery circuit based on PLL(Phase Lock Loop)structure are designed,and the layout design and post-simulation are completed.The main contents of this thesis are as follows:the CDR model established by Verilog-A is introduced,the transfer function of the CDR sub-circuit is analyzed,and the influence of different subcircuit parameters on CDR performance is simulated and compared;This thesis introduces the specific circuit structure of CDR and the basis of selecting the device parameters in the circuit,gives the simulation results and calculation process and focuses on the analysis of the influence of the non-ideal factors of the charge pump and VCO(Voltage Control Oscillator)on the output data jitter performance of CDR;This thesis introduces the advantages of FDSOI 22 nm technology devices compared with bulk silicon CMOS technology devices and explains the matters needing attention in designing high-speed circuit layoutμsing FDSOI technology.The innovation of this thesis is as follows:a high speed and low power BBPD(Bang-Bang Phase Detector)based on static D-latch is proposed,which occupies an area of 0.03×0.04 mm~2,when the circuit is locked and the input data rate is 20 Gbps,the power consumption of BBPD is 3.35 m W;A broadband low-power VCO with substrate voltage regulation frequency is proposed for FDSOI process.The frequency regulation range is 18.68 GHz to 21.8 GHz.When the output clock frequency is 21.8GHz,the phase noise of VCO at 1MHz is 101.8 d Bc/Hz,the power consumption is 3.1m W,and the corresponding FOM(Figure of Merit)value is 187.3 d Bc/Hz.The effective chip area of the CDR is 0.25×22 mm~2and the power consumption is about 8.96 m W.The simulation results show that the lock-in time is 2μs,the output clock jitter is 1.26 ps,and the output data jitter is 1.04 ps when the PRBS8(Pseudo Random Binary Sequence)NRZ(Non-return to Zero)data is input at 18.3 Gbps under0.8 V supply voltage;When the NRZ data of PRBS8 is input at 21 Gbps,the lock time is 0.6μs,the output clock jitter is 0.92 ps,and the output data jitter is 0.7 ps.According to the simulation results of different process angles,the CDR circuit achieves the expected performance index. |
