Research And Design Of Low Jitter And High Speed Clock And Data Recovery Circuit

The development of digital information technology makes the transmission of high-speed data gradually occupy the mainstream of the communications market.As an important part of the receiver,the CDR circuits are widely used in serial communication systems due to their advantages of high signal recovery quality,low circuit power consumption,and easy integration.So it is widely used in serial communication systems.However,as the data rate continues to increase,the amount of data that needs to be processed in the same time period increases exponentially,which will cause the jitter performance of the data signal to decline,and affect the quality of data transmission.Therefore,the design of low jitter CDR circuit is very important for data transmission.This dissertation focuses on the jitter characteristics of CDR circuit.The main works are as follows:(1)Research and design a low-jitter reference-less CDR circuit based on phase-locked loop.The proposed CDR circuit is mainly composed of a half-rate phase detector,a data synchronization unit,a demultiplexer,a loop filter,and a dual-loop voltage-controlled oscillator.To solve the issue of excessive data jitter caused by the unsynchronized initial input signal,the frequency adjudication unit and the data synchronization unit inside the phase detector is added to adjust the data sampling points.Besides,the initial phase error within the device is corrected to reduce the data jitter.Under the TSMC40nm CMOS process,Virtuoso is used to simulate and analyze the design.The proposed CDR dissipates 134 m W under 1.0 V supply voltage,and it completes the task of data recovery between 8.5Gb/s and 10 Gb/s.At 10 Gb/s,the recovered data random jitter is 0.344 ps_rms.And the jitter tolerance is 0.42 UI_pp.(2)To solve the issue of excessive data jitter due to insufficient phase detection accuracy during high-speed data transmission,this paper proposes a 10 Gb/s?12.5 Gb/s low-jitter reference-less CDR circuit.It is composed of a unit interval adjuster,a multi-stage half-rate phase detector,a charge pump,a loop filter,and a ring voltage-controlled oscillator.Multi-stage half-rate phase detector is used to achieve fine quantization of clock phase and data phase.A differential symmetrical charge pump is adopted to convert the current in proportion to the output level of the multi-stage half-rate phase detector.The unit interval adjuster and the loop filter are used to control the clock phase,so that the clock and data jitter is greatly reduced under different phase errors.These blocks ensures that the data jitter is always kept at an extremely low level.Under the TSMC 40nm CMOS process,Virtuoso is used for simulation verification.The proposed CDR dissipates 86.3 m W under 1.0 V supply voltage.At 12.5 Gb/s,the recovered data random jitter is 0.302 ps_rms.And the jitter tolerance is 0.46 UI_pp.The two CDR circuits designed in this paper have good jitter performance.The data jitter is small and the jitter tolerance is high.Both the pre-simulation and the post-simulation are well matched,They are very suitable for the receiver end with strict data jitter requirements.