Research On Jitter Simulation Technology Applied In High-Speed SerDes Chip

With the rapid development of processor performance and communication technology, the demand of data transmission rate increases highly and highly. SerDes has replaced the traditional parallel transmission and become the mainstream of high speed serial interface. In the design of high-speed SerDes chip, the designers need to pay closest attention to jitter. Do the research on jitter simulation technology is to simulate the design of SerDes accurately and verify its anti-jitter performance, with the result of an excellent Ser Des chip.In this paper, the structure of Ser Des is studied firstly, and then followed by various factors that impact the anti-jitter performance of SerDes such as transmission lines, packaging pins, input signals. Model them and add the model to the simulation; then according to the simulation results, researched the CDR circuit and pre-emphasis circuit, in order to improve chip anti-jitter performance; finally completed the back-end design and physical implementation of SerDes chip, tape-out successfully.Jitter simulation technology is the mainly study of this thesis. This paper has established the jitter model of the input clock and data signal, transmission line and package pin with Verilog-A language; and simulate the design of SerDes with these models and HSPICE; then complete the design of CDR and pre emphasis circuit with Cadence Virtuoso, improving the jitter tolerance of the SerDes chip; finally sign-off the layout of SerDes with Mentor Calibre.The design that simulation passed has been implemented based on SMIC 0.13 um Mixed Signal CMOS technology, the jitter tolerance that the design realized is 0.25 UI.