The Design And Verification Of The Clock Data Recovery Circuit In SerDes

With the development of technology, computational processors, computing speed has greatly improved. To enhance the quality and speed of data transmission has become an important way to improve overall system’s performance. And the popular parallel interface technology has become one of the major bottlenecks in I/O technology. To solve this problem, SerDes—the serial communication technology mainly used in fiber optic communication--has gradually replaced the traditional parallel bus, will become the mainstream of high-speed interface technology. Clock & data recovery circuit is the core of a SerDes System, i.e. to separate the data and clock signal from the input data stream, then to eliminate the jitter and distortion caused by the transmission process, deserialize the data and transfer it into the subsequent circuit after.Clock and data recovery circuit determines overall SerDes system’s performance. This essay will discuss the principles and design of CDR circuit, system-level simulation and layout design. This essay designs a 0.13μm 1P8 M CMOS fabrication based CDR circuit, uses phase interpolation based structure to replace the traditional PLL-based method, which solves the problem of bandwidth tradeoff. The design uses plenty of digital circuits, reducing the dependence and sensitivity on fabrication.The main contents of this study include:(a) The measurement of clock and data recovery circuit’s performance; The jittertransfer function, jitter generation and jitter; Jitter tolerance is a key factor tomeasure the performance of CDR circuit;(b) Use PI structure to design the circuit by dividing it into sub-module, and geteach module separately simulated, which is a key part of this kind of CDRcircuit. This study describes mathematical models of every units of a phaseinterpolation based CDR circuit, and a detailed circuit analysis;(c) Build a jitter model to study how the clock’s phase changes with jitter. UseVerilog-A to achieve the PRBS sequence generation, and use it as the testingdata inputting the CDR system to get the jitter tolerance. Get the jitter toleranceof the design via system-level simulation;(d) Study the the factors affecting the performance of the layout. Describe themethods to solve the bad effect such as antenna effect and latch effect. Identifythe precautions of layout design, and display the layout of the design in thispaper.The design goal for jitter tolerance is less than 0.4UI, and the power waste less than 500 mW. This essay gives a circuit that fully meets the above targets.