Design Of CP PLL For 1.6-2.5Gbps Clock Data Recovery Circuits

Clock data recovery (CDR) circuit is an essential ingredient of SerDes I/O chips. As a part of CDR, phase-locked loop (PLL) can generate clock signal, cancel clock distribution delay and improve system synchronization. The design of PLL gains its difficulty since the higher output frequency demands low jitter performance. However, parameters of PLL must be set conservatively due to the process uncertainty and disadvantages of traditional design. So a new structure is needed in which the bandwidth could track the reference frequency dynamically and the damping factor is established more credible.In this thesis, a charge pump PLL is designed for 1.6-2.5Gbps CDR circuits using Shanghai Hua Hong NEC 0.13μm CMOS technology. The whole PLL is composed of a digital phase-frequency detector, two identical charge pumps with differential input and single-ended output, a self-biased module which could bias the whole PLL dynamically, a 4-stage ring oscillator using differential buffer delay stage with symmetric loads, a differential to single convertor which could also adjust duty cycle, a integer frequency divider of which the dividing ratio is fixed to 10 and a startup module to confine the PLL in working condition. In this design a self-biased topology is applied to fix two essential parameters, the damping factor and ratio of natural frequency to reference frequency, which are both settled by the ratio of two capacitors. Besides, the self-biased structure can provide internal bias dynamically without external bias circuits. In this thesis both circuit design and layout are completed and simulations are run separately when temperature/process corner is 125℃/SS,27℃/TT,-40℃/FF with general terms of 2.5V supply voltage and 80MHz-125MHz reference clock frequency. Result shows that the maximum peak-peak jitter is 6.40ps@1.25GHz and 7.62ps@0.8GHz and maximum average current consumption is below 8.1mA. Layout area of PLL is 0.05mm2.The performance of self-biased PLL meets the preset standard and the PLL is completely applicable to the high speed SerDes I/O circuit.