Researches On The Key Technologies Of The High-Speed SERDES Interface Chip Design

High speed communications data systems are hot researches with thecommunication technology progress nowadays, furthermore, the research about the highspeed SERial and DESserial (SERDES) interface chip is a important part. SERDESchip mainly converts low speed parallel signal to the high speed serial low voltagedifferential signal (LVDS), meanwhile, it can receive the LVDS and convert that to theTTL signal correctly.While the high speed signal is transferred in Printed Circuit Board (PCB), any tinynoise will deteriorate the signal and increase the jitter of the signal, which make the eyediagram of the signal deteriorated and the receiver cannot receive the data correctly.Therefore, the jitter of the high speed system is one of the most pivotal fields; itincludes the jitter generation and the jitter restriction. There are two subjects about thejitter of the SERDES chip; one is the simulation methodology of the SERDES system,which is being focused recently. Although many researches are being reported, almostall the works are done by modeling the function of the SERDES system with theVerilog-A. The other is design of the receiver with high jitter tolerance, which includesa low jitter PLL, the high gain equalizer, and the low delay clock and data recoverycircuit (CDR).Based on the background of the researches of the SERDES chip, the work focuseson the design of the circuits to decrease the jitter of chip.1. While power supply is low enough, the frequency-voltage tuning range of theconventional VCO is too narrow to be applied in the applications that need broadvoltage tuning. An improved fully-swing cross coupling VCO that adapts activeinductance load is designed in the work. Its voltage tuning range is large enough evenwith low power supply, which provides a good phase-noise performance. The testresults of the chip show that the VCO can be work well in low power supplyapplications.2. The conventional voted circuit is designed by NAND logic. Once the voted signals are too much, the voted circuit needs many serial-MOS, which leads to the largetransmission-resistance and large transmission-delay, especially it is used in the lowpower supply application. A novel voted circuit is designed to get lowtransmission-resistance and small transmission-delay while it is used in low powersupply application. The test results show that the jitter of the recovery clock that basedon the voted circuit is good enough for the applications.3. Because the load of the conventional equalizer is inactive resistance, the value ofthe resistance must keep small to get broad band, which decreases the high-frequencygain of the equalizer. A novel equalizer of the LVDS with active inductance and twobias-voltage control method, which improves the gain ratio between high frequency andlow frequency of the equalizer. Simulation results show that the high frequency gain ofthe improved equalizer is larger than that of the conventional equalizer while the circuithas equal capacitance load.Finally, a receiver of the SERDES interface chip is fulfilled based on the circuitsmentioned above. It is designed with0.13m CMOS process and can transfer the dataratio from0.5Gb/s to1.5Gb/s. While received the data ratio is1.5Gb/s, the recoveryclock is750MHz and has good jitter performance.