Research On Key Technologies Of Clock And Data Recovery Circuit In High-speed SerDes

With the rapid development of Internet information technology,the requirement of speed and quality of data information transmission is getting higher and higher.At present,the development of large-scale integrated circuit makes the ultra-high speed data transmission gradually become a reality,among which the high-speed serial transmission technology,namely the SerDes interface technology,emerges at the historic moment.Because of its own remarkable advantages,it slowly replaces the original parallel transmission technology and becomes the mainstream of today’s transmission technology.The clock data recovery circuit in the receiving end of high speed SerDes system is the key module of the whole receiver circuit,which is responsible for recovering the original data from the signal after the channel.In this thesis,a clock data recovery circuit for high speed SerDes system is designed by GF180nm technology.The circuit structure based on phase-locked loop is adopted,which has better jitter suppression performance.At the same time,in order to reduce the overall power consumption of the circuit and meet the design requirements of low power consumption,the original double-loop structure is designed into a single loop structure which combines frequency discriminator and phase discriminator.The single-loop structure can not only greatly reduce the overall power consumption and area of the circuit,but also avoid the shortcomings of the frequency detection loop and phase detection loop interference with each other in the double-loop.In addition,in order to achieve better jitter performance,this thesis uses the LC negative resistance oscillator with better phase-noise performance as the clock generation module,and uses the way of multiple weight capacitors to achieve a wider output frequency range under the condition of low VCO gain.Thus,it overcomes the shortcoming of long loop locking time in single loop structure and avoids the risk of loss of lock.In order to prevent the influence of external power on the performance of the whole circuit,a linear voltage regulator with low voltage difference is designed for the clock data recovery circuit.The circuit has the characteristics of low noise and high power rejection ratio.The clock data recovery circuit designed in this thesis works at 1.8V power supply voltage,and can recover 3Gbps data signal and 1.5GHz clock signal stably.The power consumption of the whole circuit is 24mW and the layout area is 918μm×452μm.The peak-peak jitter of recovered data is about l1ps,and the phase-noise of the clock is-124dBc@1MHz.The low-voltage differential linear regulator completes the voltage conversion from 5V to 1.8V.The power supply rejection ratio is-77dB@1Hz,and the point noise at 10kHz is 77nV/Hz^1/2.