The Research And Design Of Clock And Data Recovery Circuit For1394B Serdes PHY

:As the time for the era of mass data coming,with nearly ten years the high-speed serial communication technology rapid development,now the high-speed serial communication technology can be seen everywhere in our daily life,such as USB,PCI-E,IEEE1394,Thunderbolt,etc.IEEE1394is often used in dara transmission of industrial camera,military and aerospace.IEEE1394serial communication protocols, the first time is to use on the Fire Wire of Macs.Then it is adopted and specified by the IEEE, so also known as IEEE1394.There are four layers in the IEEE1394serial communication protocols:physical layer, link layer, processing layer and the bus management.IEEE1394a,the earliest version of IEEE1394,in the Backplane mode support12.5,25,50Mbps transmission rate, and Cable supports100Mbps,200Mbps,400Mbps.IEEE1394b,reached800Mbps and extended the transmission distance with the original4.5m to50m in Cable mode.And in2007,IEEE1394c supported1.6Gbps and3.2Gbps.This paper is about the research and design of CDR(Clock and data recovery) for IEEE1394b.The core function of CDR is to receive and retime transmission data. Whether it can work normally directly affects the overall performance of the chip.At first,this paper introduce jitter and data coding types,focus on the clock-generate model with jitter and data-generate model for CDR simulation.After comparing different types of CDR,this paper selects PI-based CDR for IEEE1394b PHY.The linear model of PI-based CDR,included Alexander PD,digital loop filter,phase interpolation circuit,is introduced.Then this paper detail introduces how the gain of the proportion path and the gain of integral path affect the transmission function and the jitter tolerance curve,and the design and simulation of CDR.Finally mixed-signal circuit layout design considerations and the test results are introducedThe structure of CDR used in this paper is PI-based CDR,supported S800,S400,S100data transfer mode.Using PLL to produce four phase clock((0°,45°,90°and135°) for CDR,the resolution is π/32,and the maximum operation frequency is1GHz,1.2V supply voltage.Finally using Cadence EDA tools to finish the schematic and layout design,and the chip was taped out in SMIC0.13u MPW process.