The Key Circuit Design Of FT-SerDes CDR

Serializer / deserializer(abbreviated Ser Des) is a kind of integrated chip transceiver module. The interconnection between the chip serial data transfer, is through the Ser Des conversion data transmission between serial and parallel port in each direction, and vice versa. It is used in high speed data communication system, to make up for the limited input / output port number in the differential data transmission, and improve the anti-interference ability of data, reduce the I/O pin and the interconnection line. Ser Des technology is the mainstream of today's data transmission mode.In this paper, the design of the two times of sampling, data alignment and data demux, phase detection of sampling clock, two order digital filter, data coding, and DAC and PI circuit module. The specific work includes the following aspects:1.The use of two times of sampling design of sampling circuit, sampling differential data, the sample data including the clock information. For each of two consecutive bits of data acquisition of four samples, two edges and two data information,to restore the synchronous clock. In order to make the difference data into a single terminal data, added a two terminal data to single ended conversion circuit, the Latch circuit with special structure. In order to overcome the sampling of the metastable state data, an increase of two stage sampling module. Using Hspice simulation sampling circuit function verification, two sampling structures can overcome metastable sampling with Spectre simulation..2.In order to realize the parallel processing of sampling data, design data alignment and data deserializer circuit. By aligning circuit data, two kinds of data sampling, data information and edge information of data, data alignment. Alignment of data after the DEMUX circuit two special, namely DEMUX 2:4 And DEMUX 1:5 data, data information and edge information are converted to 20 bit parallel data. The use of Hspice simulation to verify the data is aligned with the DEMUX circuit, the data rate can be the right solution on 2.5Gbps. And through the hybrid simulation of NC-Verilog for FT-Ser Des system..3.Through the design of phase detection of two order digital filter, using the clock information contained in the sample data, extract the synchronous clock. The mathematical model is set up to two order digital filter, and use Matlab to verify the performance of the model, which can meet the Jury criteria[1][2] stable triangle, the realization of the two order digital filter in the step response and stability. In the circuit design, the use of Bang-Bang[3][4]algorithm to detect the phase of the clock phase,determine the sampling clock is ahead or behind the data center point position. Through the Vote Majority(the majority voting machine) the phase detection. The use of FSM(finite state machine) output on the Vote Majority(cyclic addition and subtraction ofintegral process), get the quantization error of the sampling clock phase and the ideal clock phase. The AMS hybrid simulation, to achieve a clock phase tracking, correctly received data.4. The data coding circuit, realizing the conversion of the output of the two order digital filter capacity, control of DAC and PI(Phase Interpolation)[5][6][7]. Through the coding circuit design, the 10 bit quantization error into 3 groups of 27 pairs of differential digital control signals. The accuracy of DAC in the control and interpolation of the 8 phase clock selection, selection of the two-phase clock adjacent interpolation.The use of Spectre simulation to verify the encoding circuit function.5. In phase with the data center to adjust the sampling clock position, through the use of DAC control PI circuit, before and after the realization of clock phase adjustment.Special DAC circuit design in the current source control, 4bit conversion precision,resolution LSB(28)1/16. INL(integral nonlinearity) and DNL(differential nonlinearity),-3LSB(27)INL(27)2LSB,-0.5LSB(27)DNL(27)0.5LSB, satisfy the monotone linear DAC transform. Design of PI circuit, phase interpolation on the two clock, the clock is a weighted sum of two clock, the output clock phase between two input clock phase. The dynamic range of the coverage of the entire cycle phase interpolation. In the interpolation weights, clock, meet, phase control precision is about 2.8 degree. The use of AMS on DAC and PI hybrid simulator, the simulation is realized, the monotone linear interpolation clock phase change.