The Design And Implemention Of A Clock And Data Recovery Circuit Based On 65nm CMOS Technology

With the increasing progress of information technology,high density computing,network communications,dense image processing and mass data transmission requirements of the bandwidth of the I/O port and the transmission speed of the chip is getting higher and higher.Clock and data recovery(CDR)circuit is the key module in the Serdes system,which restricts the maximum transmission rate of Serdes.The CDR circuit is responsible for recovering the clock and data signal from the received serial data stream that does not contain the clock.This paper designs and implements a 8Gbps clock and data recovery circuit,which is based on 65 nm CMOS technology applied to the Serdes IP core.The work of this paper is divided into the following aspects:Firstly,the circuit level design of CDR is carried out.The main technical points from the following aspect: Select the PS/PI type structure that can quickly capture and stability;Multi structure design analog module is used to improve the working frequency of the system;Design of two order digital filter to solve the frequency difference tracking problem;CDR support three operating modes of the half rate,full rate,double rate.Support data rate is 1.25/2.5/3.125/6.25/8Gbps,The main circuit consists of PI,duty cycle adjustment loop,high speed sampling,serial parallel conversion,mode conversion,second order digital filter.Secondly,after the CDR circuit design and the pre-simulation,the layout design of CDR is carried out.Phase interpolation module is the most important module in the CDR circuit,also belong to the noise sensitive circuit,using the deep n-well process to achieve PI layout.The layout area of the mode conversion module is 200 ?m * 120 ?m,the total area of the other modules is 820 ?m * 360 ?m.The area of deep n-well is 160?m * 260 ?m.The area of the second order digital filters is 440 ?m * 360 ?m.Finally,the simulation and analysis of the design are carried out.CDR circuit and layout in different conditions of the input data rate,the clock and data can be recovered correctly.The power consumption of the circuit is 76.7 mW.post-simulation shows,when the input data is lower than 6.25Gb/s,recovery data eye opening more than0.88 UI.When the input data is 8Gb/s,eye opening 0.751 UI.Adding 500 ppm frequency difference in input data,CDR can track.Adding 2MHz jitter in the input data,the deterministic jitter of the recovered data is less than 0.3UI.PI pre-simulation display,the bandwidth of PI is 7.6 GHz,the maximum value of DNL is 0.5°,and the INL is 3°;Post simulation shows that the DNL value is less than 1.3°,INL value is lower than 4°.When the input differential mode signal is higher than 30 mV,data can be restored correctly.