Optimal Design Of Clock And Data Recovery Circuit For 40Gb/s SerDes

Due to the non-idealities, the traditional parallel communication technology encounters the bottleneck in the ultra-high speed application, and is gradually replaced by the serial communication technology, which has higher transmission speed and lower cost. The clock and data recovery (CDR) circuit is the core component of the receiver. It extracts clock signal with low jitter from the received data stream with jitter to provide the clock signal for the subsequent circuits. And it also retimes the data stream by the clock signal to recovery the data signal with clear eye-diagram for the further processing.A 40Gb/s half-rate Bang-Bang CDR based on PLL is designed in TSMC 65nm LP CMOS process, including quadrature voltage controlled oscillator (QVCO), half-rate Bang-Bang phase detector (BBPD), loop filter, buffer and so on. The design goal is to reduce the power dissipation based on area decrease, which makes the optimization from the selection and improvement of the structure and parameter. The jitter performances of Bang-Bang CDR are analyzed in the paper. The relationship between jitter transfer, jitter tolerance, jitter generation and the loop parameters is also derived in detail, and the design process of the Bang-Bang CDR is proposed. The QVCO is consisted of the LC-VCO based on the cross-coupled NMOS devices and biased by the tail current to reduce the parasitic parameters and work at higher frequency. The Q value of the LC resonator, the tunning range and linearity of the VCO are optimizated. The half-rate BBPD is improved to enhance the symmetry of the load of the orthogonal clock signal and reduce the load capacitance of the orthogonal clock signal. The pseudo differential latch is used to improve the speed, and the high threshold transisitor is used to cascade the circuits. In addition, the D-Flip-Flop of BBPD is improved to reduce power consumption and enhance the speed. Fully symmetric CML XOR is adopted in BBPD to eliminate the asymmetry of the path of the two input signal, which also forms the symmetric current relaying structure with current comparator replacing the traditional voltage relaying to improve the speed. In the layout, the deep N-Well is adopted to minimize the coupling and interference of the noise to optimize the jitter performance.The post-layout simulation is showed that the QVCO can be tuned from 19.37GHz to 20.71 GHz and achieves the phase noise of-102.53dBc/Hz at 1MHz offset from a carrier close to 20GHz, and the phase difference of the orthogonal clock signal is 90.95deg. In addition, the CDR achieves the clock recovery and 1:2 data demultiplex correctly, furthermore the clock and data jitter of CDR are 1.844ps (0.037UI) and3.146ps (0.063UI) respectively.