Key Technique Research And Design Of Energy-Efficient Low-Jitter Clock And Data Recovery Circuit

As the demand of high-speed serializer/deserializer(SerDes)link for transmission distance and transmission rate continues to rise,the problem of transmission signal dis-tortion and bit error caused by channel non-idealities has become increasingly serious,while clock and data recovery(CDR)circuit used to solve the jitter issue in received data,is the key block to determine the bit error rate(BER)performance of high speed SerDes system.In addition,the rise of Internet of things(IoT)application makes the chip with high energy-efficiency become the key competitive factor of product.We focus on CDR circuit and their building blocks,studying the key techniques of high energy-efficiency and low jitter design.The theoretical analysis and chip measurement are both well verified.The main function of CDR circuit is to recover the clock signal from the input data and then use the recovered clock to re-timing the distorted data,which jitter performance is the most concerned.The prior works often reduce jitter at the cost of larger power or more complex circuit,whereas this paper proposes a compact quarter-rate single-loop CDR circuit.By combining both the quadrature voltage-controlled oscillator(QVCO)and phase interpolator(PI)in the same CDR loop,the multi-phase clock generation loop needed for the dual-loop architecture is eliminated,thus reducing both the circuit complexity and the extra source of power consumption and jitter.At the input data rate of 10.3125Gb/s,the peak-to-peak jitter of the recovered clock and data are 1.14ps and 1.21ps,respectively.The total power consumption at 1.1V supply voltage is 4.8mW,while the corresponding energy efficiency achieves 0.47mW/Gb/s.The occupied chip area is 0.55mm2.In addition,this paper proposes a peak-injection coupling technique for the QVCO.By controlling the coupling current and injecting current only at the most non-sensitive peak position for LC-VCO's phase noise,the coupling current and its de-terioration of phase noise performance is minimized compared with the conventional parallel coupling structure.The phase noise at 2.6GHz is-121.6dBc/Hz,and the power consumption is 3.63mW,while the corresponding FoM achieves 184dBc/Hz.The pro-posed CDR circuit,QVCO and other main blocks are all verified through simulation and some measurement in SMIC 40nm CMOS process.Frequency divider(FD)is used to provide the reference clock signals with the required frequency and phase relationship for CDR circuit.Typically,multi-standard high-speed SerDes systems are integrated in a single chip,so that high-speed FD must be designed with wide-band programmable features;To save power consumption and die area,a shared clock generator for multi-channel CDRs is generally preferred,and therefore low-power FD with at least quadrature output phases is demanded.The prior designs usually sacrifice large power for high speed,and cannot achieve programmable quadrature output signals at high speed,whereas this paper proposes a cascade structure of programmable FD and quadrature FD.The lower frequency signals generated by the programmable FD are then processed by a quadrature FD to reduce the design difficulty of quadrature output with low power consumption.In addition,this paper proposes a sense amplifier based flip-flop(SAFF)for programmable FD,which improves the power consumption and delay performance by adopting dynamic latch with enhanced positive feedback,and realizes high-speed operation with low power consumption.The maximum operating frequency is 14.8GHz,and the power consumption at 1.1 V supply voltage is 0.54mW,while the corresponding energy efficiency achieves 27.38GHz/mW.The proposed programmable quadrature FD is verified through measurement in SMIC 40nm CMOS process.Voltage reference(VR)is used to provide the desired reference voltage signal not varying with process,supply voltage and temperature(PVT)for CDR circuit.With the rapid growth of system-on-a-chip(SoC),high-speed SerDes system requires that VR circuit should have good power-supply noise rejection and ensure the stability of refer-ence voltage over a wide temperature range;As CDR design continues to evolve into deep sub-micron process,VR circuit should be capable of operating at 1V or less sup-ply voltage;In addition,the increasing mobile electronic devices make low-power VR design become necessary.The existing structures always cannot take into account low power,low temperature coefficient(TC)and high power-supply rejection ratio(PSR-R),whereas this paper proposes a high-performance sub-threshold CMOS VR circuit.By using low voltage cascode structure with enhanced negative feedback,the power supply noise suppression ability of proportional-to-absolute-temperature(PTAT)sub-threshold current is guaranteed.The worst PSRR can reach-55.0dB @30kHz.At the same time,through in-depth analysis of the negative TC of VGS in subthreshold region,the temperature compensation of VGS is performed with the PTAT current flowing into it.The average TC achieves 19.1ppm/? @-40?-120?.The total power consumption at 0.7V supply voltage is 8.9?A.The proposed CMOS VR circuit is verified through measurement in SMIC 40nm CMOS process.