Research And Design Of A2.5Gb/s PS/PI-based Half-Rate Clock And Data Recovery Circuit

Rapid growth of computation capability of microprocessors has driven the need for wide-bandnetworks and high-speed communication systems. Serial communication architectures take theplace of traditional parallel architectures in the domain of short-distance I/O communicationsystems, and get a widespread application. As the key part of high-speed serial communicationsystems, a CDR circuit plays the role of extracting a synchronized clock signal from the distorteddata stream, and retiming the data to remove the distortion and jitter in it.With analysis of classic CDR circuits theory, including operating principle, architectures,performances, this dissertation introduces a PS/PI-based half-rate CDR circuit implementationbased on standard SMIC0.18μm CMOS process, whose working data rate is2.5Gb/s. With dualloop topology is adopted, this dissertation forcus on phase tracking loop design, including ahalf-rate Bang-Bang phase detector, a PS/PI circuit, a digital filter, a digital controller,etc. Ainterpoation weight controlling compensation is used to decrease nonlinearity, and the revised PS/PIgenerates two differential in-phase/quadrature clocks by means of two PS circuits and two PIcircuits, which, compared to a traditional one, has two less PS circuits and reduces its complexityand power. Besides, Verilog behavioral modeling is applied with the digital filter and digitalcontroller, then using EDA tools automatically synthesizing, placing and routing to generatetransistor level and layout level circuits, so the design complexity is reduced compared to analogdesign flow.The whole design occupies0.825mm2. Simulation results show that with an PRBS input of2.5Gb/s, the peak-to-peak jitters of the recovered clock and data are18.6ps and21.1ps,respectively， and the power consumption is72.4mW, which can meet the requirements ofshort-distance I/O interfaces.