Research And Design Of Clock And Data Recovery In High-speed SerDes

With the increasing traffic demand,the traditional parallel interface technologies required for its excessive number of pins and gradually phased out and replaced by the original used in optical fiber communications serial communications technology--SerDes(Serializer/Deserializer).Due to the space level Ser Des IP core products belong to the strict embargo products abroad,radiation-hardened SerDes has become the future main bottleneck of high performance informat ion processing device application restrictions..Therefore,designing radiation-hardened Ser Des IP core independently is very meaningful.Clock and data recovery(CDR)circuit is the core of the SerDes system,and restricts the key to its performance.Therefore,based on 65 nm CMOS process,this thesis completed the research and design of the CDR which is the key block of SerDes.In this thesis,starting from MATLAB modeling,mathematical model of in-depth study CDR works,then under the guidance of the model,complete the corresponding circuit design and layout design.This thesis designed a dual-loop CDR based on phase inpterpolater,one of the loop is PLL,and the other one is DLL.The DLL is consists of phase interpolater,high-speed sampler,demux,edge detector and second-order digital loop filter.Supporting a wide range of operating speed of 1.25 ~ 6.25 Gb/s and half rate,full rate,double rate,three modes which reduced the difficulty of designing a PLL.Furthermore,its bandwidth is programmable and it is able to tolerate certain frequency offset.In addition,the phase interpolater is realized by 7 bit structure.In order to increase the speed of locking time when there is a frequency offset,this thesis has innovatively added a fast-locking algorithm in the second order digital loop filter,and its locking speed is increased twice as much as the traditional's when the frequency offset is 1000 ppm.It makes it having the capability to meet the requirements of bursty data transmission system.As the simulation results shows,at the working speed of 6.25 Gb/s and the 1.2 V power voltage,the jitter transfer bandwidth of C DR can programming from 2 MHz to 7.5 MHz,the maximum frequency offset is ±1800 ppm,the eye width of the data is wider than 0.89 UI when the frequency offset is 1800 ppm and the power consumption is less than 16.4 mW.In addition,the DNL of the PI is 2.8o and its INL is got 7.2o.The simulation results meet the system design specifications.