Design Of Clock And Data Recovery Circuit For 40Gb/s Serdes

With the development of information age,people have higher requirements on data transmission rate.In high-speed data transmission,parallel transmission is gradually replaced by serial transmission due to various non-ideal factors.Ser Des as the mainstream of high-speed serial communication technology is widely used in high-speed data transmission.As the most important module of receiver in Ser Des,clock and data recovery circuit directly determines the maximum transmission of communication system and the quality of transmitted data.In this paper,the 40Gbit/s clock and data recovery circuit is designed in 40nm CMOS process.The main modules of the circuit include half-rate Bang-Bang phase detector,V/I converter,low pass filter,quadrature voltage controlled oscillator and buffer.The jitter performances of Bang-Bang CDR are analyzed in detail,and a jitter model of nonlinear CDR is constructed to guide the design of Bang-Bang CDR.The Bang-Bang phase detector with half-rate structure is more suitable for circuits in high speed.The quadrature LCVCO with low phase noise is helpful to reduce the jitter of the recovered clock and data.The current mode logic latch is used to improve the speed of phase detector.Symmetric CML XOR is adopted to reduce the error of phase detector due to the different path delays.V/I converter and XOR are combined and the current signal is transmitted through the current mirror.In this way,V/I converter can work at a higher speed.In order to reduce the influence of electricity loss distribution,the parameters of V/I converter are optimized.A three-stage current mode logic buffer is adopted to improve the driving ability of the VCO.This thesis presents the circuit design,layout design,the pre-simulation results and the post-simulation results of the 40Gbit/s CDR.The core area of the chip is 0.484 mm~2.The post-simulation results show that the tuning range of the quadrature voltage controlled oscillator is 19.9 GHz-20.65 GHz.In tt process corner,when the control voltage is 0.5V,the phase noise of the quadrature voltage controlled oscillator is -99.6373d Bc/Hz@1MHz at 27?.The lock time of the CDR is 100ns.This CDR can recover two 20GHz quadrature clock signals from the input 40Gbit/s pseudo-random sequence under the supply voltage of 1.1V,and divide the recovered data stream into two 20Gbit/s parallel data streams correctly.The post-simulation results shows that the jitter of clock is 0.30886ps,and the jitter of two parallel data are 2.5584ps and 2.9461ps.