High-speed Low-power Cmos Charge Pump Phase-locked Loop Technology

In recent years,the rapid growth in wireless communications has driven the research and development of low-cost and low-power CMOS wireless transceivers. It is a great difficulty to design a high-speed, low-power RF CMOS PLL (phase locked loop), though most components of wireless transceivers can be integrated on single chip along with increasing progress in the CMOS process technology. In this thesis, a high-speed, low-power and third-order current-mode charge-pump PLL is designed according to the CDMA standard by in-depth analyzing and researching the principle of PLL.The main contribution of the thesis is seen as follows:Aiming at the fault with slow speed and high power dissipation of the conventional phase-frequency detector, a high speed and low power dissipation phase-frequency detector is designed by modifying the structure of the single phase lock dynamic D flip-flop and adding the delay cell in the feedback loop to eliminate the phase detector's dead zone effectively.Due to the charge sharing and charge leakage phenomena in the traditional charge-pump, a new charge-pump with current control technique is designed in this thesis. In the circuit design, a simple positive feedback is employed to expedite the switching speed. The simulation results show that the charge sharing and charge leakage phenomena can be effectively prohibited in the proposed charge-pump.On account of the low Q-factor and small tuning range of the p-n junction varactor, the inversion-mode MOS varactor is used in the LC voltage controlled oscillator in this thesis. The simulation results show that the designed LC voltage controlled oscillator has 15% tuning range.Contrapose to the instability of the third-order charge-pump PLL system, the loop optimization method is employed in system level design to decide the bandwidth and phase margin, therefore the loop bandwidth locates at the maximum phase margin to guarantee the stability of the system.According to TSMC 0.35μm SiGe BiCMOS model, the sub-circuits in the designed PLL and the whole system are simulated and verified by the Cadence Spectre...