Research And Design Of Key Technology Of Silicon-based CMOS Phase Locked Loop

From the "steam age" to the "electric age",the rapid development of science and technology continues to lead the progress of human society and change people's daily life.With the development and use of the current fifth-generation mobile communication technology,while improving the industrial efficiency and quality of life of human beings,it also puts forward higher requirements for transceivers in wireless communication systems.As a key module in the transceiver,the performance of the phase-locked loop circuit system is very important.For chips,the manufacturing process often becomes a key factor restricting its performance.Compared with other processes,the silicon-based CMOS process has the advantages of high integration,low power consumption,low cost,and broad development prospects.Therefore,this thesis firstly sorts out and summarizes the research and development context of silicon-based CMOS phase-locked loop and its key technologies in recent years,and introduces the basic theory,general architecture and performance indicators of the phase-locked loop system and its key technologies in detail.Finally,this thesis completes the specific circuit design of the key technology in the phase-locked loop based on the silicon-based CMOS process.Then this thesis uses 65 nm CMOS process to design a three-state linear frequency and phase detector.On the basis of the conventional structure,an enable terminal is added to reduce its overall average power consumption;at the same time,a reset terminal is added to provide the possibility of timing adjustment to improve the stability of its operation.While,a charge pump with dual operational amplifiers are designed to reduce mismatch,achieving high matching of charge and discharge currents,and reduce loop spurs.The post-simulation results show that the cascaded timing function is normal and the current matching is good.The measured phase-locked loop works normally.In terms of low phase noise voltage-controlled oscillator design,this thesis uses180 nm CMOS process to design a Class-C voltage-controlled oscillator.In the process of layout design,the coupling between the inductor and the ground plane is analyzed to improve the quality factor of the inductor and optimize the phase noise performance.The tuning range is measured from 3.65 GHz to 4.10 GHz.The relative bandwidth was11.6% and the current consumption was 6.71 m A at a supply voltage of 1.8 V.The phase noise was-127.8 dBc/Hz@1 MHz at 4.05 GHz.The measured Fo M is 189.1dBc/Hz.In terms of ultra-low power consumption voltage-controlled oscillator design,this thesis uses 65 nm CMOS process to design an inverse Class-C voltage-controlled oscillator.Its core resonator uses a drain-source feedback transformer with high quality factor to replace the inductor in the conventional structure,which greatly reduces its power consumption on the premise of ensuring phase noise performance.The measured frequency tuning range is from 4.65 GHz to 5.67 GHz,and the relative bandwidth is19.7%.The measured DC power consumption is only 187 ?W to 270 ?W in the full frequency band,and the phase noise is from-110.8 dBc/Hz to-113.2 dBc /Hz.The measured Fo M is 192.4 dBc/Hz.