Design And Implementation Of A High Speed Phase Locked Loop

Phase-Locked Loops(PLL) are circuits which can generate a steady output clock. They are used widely in analog circuits. The clock and data recovery circuits in transceiver need PLL circuits to recover the clock and data from the receive data. High speed micro processor also need PLL to generate a high accurate clock which used in the internal. The PLL have ripe structure after several decades. But the fast developing of IC needs the PLL have faster speed and lower power. So we should continue to do research on the PLL circuit.Ethernet is a wide used Local Area Network, especially the 10Mb/s, 100Mb/s and 1000Mb/s ethernet. They are mostly used in the office. The transmission distance of them is less than 100 m. But the 10Gb/s ethernet is designed to used in Metropolitan Area Network. They can transmit data in a long distance away. The transmission distance is nearly 40 km. 10Gb/s ethernet contains 4 transceiver. The speed of transceiver is up to 3.125Gb/s. The long distance transmission also waste more signal energy. All of this remand a more accurate PLL. The center frequency of PLL should be 3.125 GHz.In this thesis, we describe the basic theory of PLL firstly. Then we analyze the transfer characteristic of the PLL loop. They provide the theory of the design underside.The speed of the PLL we designed is high. So we choose the CP/PLL to achieve the design.The structure of PFD is a structure within a delay cell which can avoid the dead zone. The CP’s structure is a new differential circuit. It has op-amp to match the current mirrors, and it also has some MOSFET to eliminate the aiguille pulse. The filter is a two steps low-pass filter which are widely used. The filter can decrease the ripper on the control voltage and minish the phase noise of output clock. The VCO is a ring oscillator, realized by using four delay cells which have a push-pull stucture and have a high output voltage range and good performance on noise rejection. The SCL(source coupled Logic) structure is used in the dividers. This structure can make the dividers working in a high frequency.We use the TSMC 0.13μm CMOS technology model to do simulation. The power supply we choose in this design is 1.2V.The result of simulation satisfy the need of design.