Research And Design Of Charge Pump Phase Locked Loop Based On 0.18?m CMOS Process

The Phase locked loop can generate accurate clocks,which are used in electronic systems such as clock synchronization circuits,clock recovery circuits,and frequency synthesizers.As one of the important applications of phase locked loop,frequency synthesizers have the characteristics of stably outputting high-frequency clock signals,which are widely used in wireless transceivers,microprocessors,radars and other fields.With the rapid increase in the amount of information and data exchange,the system has higher and higher requirements for the frequency and stability of the clock signal.Therefore,the research on low-noise,fastlocking,high-frequency frequency synthesizers is of great significance.In this article,a charge pump phase-locked loop based on a frequency synthesizer was designed.Based on the in-depth study of the PLL loop structure,the S-domain linear model of the phase-locked loop system is analyzed to complete the system parameter design.In order to verify whether the system can be locked under preset parameters,MATLAB tools are used to conduct behavioral simulation of the system.Based on the parameter design of the charge pump phase locked loop system,in this paper,the PFD,CP,VCO,DIV and other sub-module circuits was designed.For the design of PFD,a set of switching circuits are added between the input signal of the frequency discriminator and the flip-flop to restore the rising edge of the input signal during the reset process,thereby eliminating the phase detection dead zone.In order to solve the non-ideal effect of the charge pump,The input Rail to Rail amplifier was used to eliminate charge sharing;The cascode current mirror was used to improve current replication accuracy;The CMOS transmission gate used as a switch to eliminate clock feedthrough,by the above method,the chargedischarge current mismatch of the charge pump is only 1%.In order to improve the driving ability of the voltage-controlled oscillator,a complementary LC oscillator with a buffer stage is designed,the small swing sine signal output by the voltage controlled oscillator is enhanced into a full swing square wave signal with a duty cycle of 50%.In order to achieve an output signal of 2.56 GHz,an integer frequency divider with a division ratio of 128 is designed,At the same time,in order to increase the operating frequency of the divider and reduce power consumption and area,the flip-flop in the divider adopts a TSPC(True Single Phase Clock Logic)structure.Based on the TSMC 0.18?m CMOS process,the pre-simulation,layout and post-simulation of the phase-locked loop are completed.The simulation results show that under 1.8V power supply voltage,the input reference frequency is 20 MHz,the PLL can stably output a clock signal with a frequency of 2.56 GHz,and the lock time is 3 ?s,and the phase noise at 1MHz frequency deviation is-119.65 d Bc/Hz.The peak-to-peak jitter is 5.91 ps and the power consumption is 11.4m W,which can meet the design specifications.