A High Performance CMOS Charge Pump PLL Design

Phase-locked loop (PLL) is a circuit which can synchronize its output signal with an input reference signal in frequency. It's a fundamental and very important module in analog and mixed-signal integrated circuits. Because of its ability of tracking, acquisition and operating as a narrow-band filter, PLL is widely used in many fields such as astronautics, communication, microprocessor, and so on. One important application of PLL in microprocessor is to provide on-chip clock for the system. It has been a very important module of microprocessor. With the development of integrated circuits and the emergence of SOC (System on Chip) technology, PLL has played so important a role in VLSI circuits that it is worth researching and designing.In this paper, the research and design of a phase-locked loop utilized in RFID Basestation system are described in detail. First of all, the history of phase locked technology and the actuality of researches on it are introduced. Then, beginning with the fundamental principles of a phase-locked loop system, we build the mathematical model. Afterwards, the design process of this project is described in detail, including the analysis and design of the phase/frequency detector, change pump, loop filter and voltage controlled oscillator, as well as the whole circuit system. And then, the system parameters are deducted. At last the circuits are simulated.The main work and innovation include: Design a new PFD circuit which is more effective then the usual one. The whole simulation is based XFAB 0.6um CMOS process. Cadence'Spectre is used to input the PLL circuit and accomplish the simulation. From the circuit structure and the result of the simulation, we can see the designed CPLL possess the characteristic of low power, high steady. The design can satisfy the RFID Basestation application.