A Design Of 10-bit High-speed CMOS Pipelined ADC

System-on-chip is the trend in current CMOS technologies, and the analog-to-digital converter (ADC), the digital-to-analog (DAC) and the DSP module are usually integrated in a single chip. With the digital signal processing technology widely applied in high resolution imaging, video processing and wireless communication, the system puts forward higher requirements for ADC, and faster, higher resolution and lower power dissipation ADCs are impending needed. The study on ADC is a current hot research topic.There exist various types of ADCs, but the pipelined ADC can do the best performance when speed, resolution, power dissipation and chip size are considered, for the partitioned nature can achieve high resolution but still remain low power dissipation.In the thesis, a 10-bit 100MHz low-power pipelined A/D converter was designed base on TSMC 0.25μm 3.3V CMOS mixed-mode process.The first eight stages used 1.5 bit/stage pipeline structure and the ninth FLASH structure in the design. Digital correction circuit was adopted to ensure the conversion result, and the rate, power consumption and dynamic characteristics were considered at the same time, and finally reached the expected goal. For the concrete circuit design, several pop circuit techniques as folded cascade OTA, CMOS bootstrapped sampling switch, and dynamic comparator with RS-trigger were used to reduce non-ideal factors like noise, distortion and mismatch. OTA sharing techniques was used to decrease the system power consumption and area. Clock duty cycle stabilizer was added to keep the stability of sampling clock.The simulation of pipeline A/D converter module by Spectre under Cadence environment was completed. The static and dynamic parameters were calculated by Matlab. The whole layout of pipeline A/D converter was given at the ending.