Research And Design Of A Low Power High Speed Pipelined ADC

In mixed signal systems, Analog-to-Digital Converter (ADC) is a crucial portion. Pipeline ADC has the advantages of high speed, high resolution, low power consumption and small area, so it is very important to study the structure of pipeline of ADC.Based on the analysis of some common architectures,this thesis presents a 1.8V 10-bit 100MHz pipelined Analog-to-Digital Converter.It's composed of a sample-and-hold circuit, eight stages with 1.5 bit per stage, and a 2 bit Flash ADC as last stage. There is a modified sample and hold circuit at the input of the ADC and the DC wandering of input is suppressed. With the bootstrapped sampling switch, the resolution and linearity of the system is improved . High speed, high gain are achieved by a single stage folded cascade opamp with gain-boosted technique consuming very low power. Besides, the following technque are taken to reduce power consumption: 1. The operational amplifier sharing technique is used to reduce the number of opamp, so the power consuming components is reduced. 2. The size scalling down technique is use to reduce power. 3. Power consumption is further reduced by using of dynamic comparator.The ADC's design is based on TSMC 0.18μm, mixed signal 1P6M process, which provides MIM capacitor. The simulation result shows: At the room temperature, 100MHz sampling frequency, it achieves SNDR(SINAD) of 59.12dB@1MHz input , 58.4dB@10MHz input, SFDR of 79.6dB@1MHz,74.2dB@10MHz; In the whole nyquist input frequency, the ENOB is over 9 bit. And the power consumption is 62.5mW.