High-precision, Low-power Pipelined Adc Research And Design,

Pipelined analog-to-digital converter (ADC) is widely used in the systems of image signal processing, base stations and digital video, fast Ethernet, ect. For hand-held mobile terminals, low power devices play a vital role for the life of the battery. At the same time, as people demanding of sensory experiences such as sound, picture quality have become increasingly and the requirement of more detailed information, design has become a very important aspect.Low power consump-tion usually tends to reduce the accuracy while high accuracy is often needed to increase the cost of power. Thus, how to achieve high accuracy and low power consumption simultaneously has become a hot research spot.This work focuses on the high accuracy and low-power pipelined ADC for digital video system. The opamp-sharing technology is used to achieve low power consumption at the cost of the resolution reduction, since the conventional opamp-sharing ADC has some serious problems. To get rid of these problems, an new architechture of MDAC was proposed to improve the system accuracy. A Matlab model of pipelined ADC which guide the actual circuit design is structured, variety of non-ideal factors are involved in the behavioral simulation. By using this MDAC, this work presents the transistor level of pipelined ADC. Finally, layout and chip testing are described.The specific research contributions of this work include:1) Starting from reducing the power consumption of the opamp telescopic opamp was selected for its lowest power consumption. More methods such as opamp-sharing between successive stage and stage-scaling-down were adopted to achieve low-power design.2) To get rid of the problems of memory effect, successive stage crosstalk, charge injection and clock feedthrough, a switch-embedded MDAC with dual NMOS differential input pairs current-reuse OTA is proposed.3) The dual NMOS differential input pairs was proposed to eliminate the memory effect. Since both input pairs are reset to a common-mode input voltage alternately, the memory effect is completely eliminated without any additional clock phase.4) By embedding the opamp-sharing switches into OTA, the effect of the inter-stage crosstalk path, charge injection, clock feedthrough and the offset introduced by parasitic resistance of opamp-sharing switches ware eliminated and does not affect the signal settling accuracy. The embedded switches only consumed about 30mV of votage margin, so not affect the opamp's output swing.5) The two-phase non-overlapping clock is always used in a pipelined ADC but is not suitable for controlling the opamp-sharing switches in the proposed OTA. To achieving a well matching, a optimized stable high-swing bias circuit is employed for the OTA.6) Based on the signal transfer function, A Matlab model of pipelined ADC is structured to guide the circuit design. By involved the effect of many non-ideal factors such as mismatch, noise, GBW, slew rate, jitter and offset, this model is reasonable according the silicon results.7) In the SMIC 0.18-μm,1.8V supply voltage, single-poly six-metal standard CMOS process, the circuit and layout design, simulation and chip testing of a 10 bit 80MSps pipelined ADC are completed.By using the proposed switch-embedded opamp-sharing MDAC based on a dual NMOS input pairs current-reuse opamp, an improved accuracy is achieved without any additional power and area consumption and clock phase.Further more, built on the good isolation characteristic of the dual-input switch-emmbeded opamp, a new circuit structure of opamp-sharing between S/H circuit and the first MDAC stage was proposed to significantly reduce power consumption by avoiding the extra power consumption of opamp.The ADC achieves a peak ENOB of 9.69 bit and a peak SFDR of 76 dB, while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth. When input frequency is close to sample rate, the ADC still maintains 9.47 ENOB. When sample rate rises to 100MHz, there is still 9.1 ENOB. The chip consumes 28mW an FOM achieves 0.42 pJ/step. The measured SNDR and SFDR are better than other recently published works of 10-bit pipelined ADCs on JSSC, ISSCC and CICC, and FOM has achieved a higher level. This work can be used in low power consumption and high accuracy digital video system an embedded in applications of SOC.