Optimization And Research On High Speed Pipelined Analog To Digital Converters And Digital Calibration Technology

Analog-to-Digital Converter(ADC)is the key bridge between digital and analog systems.Based on the standard digital integrated circuit technology,performance optimized ADC is an important building block as the important interface of SOC systems.Various architectures such as Flash,Folding and interpolating,SAR and others have been used.Among these architectures,the pipelined A/D converter is the most efficient one for applications in high speed and medium or high resolution signal processing and communication applications.High performance pipelined analog to digital converters is always used extensively in high speed data acquisition systems as it offers a better trade-off between resolution and power.Because of mismatch in manufacturing process or theoretical error in analog design,pipelined A/D converters have some non-ideal effects such as comparator voltage offset,front-end network mismatch in SHA-less structure,sampling capacitor mismatch,operational amplifier finite open-loop gain error and offset error,amplifier non-linear effect.Although some non-ideal effects can be tolerated as comparator offsets through the use of redundancy,capacitor mismatch,residue amplifier gain,and nonlinearity severely limit the conversion accuracy.A high speed,medium precision pipelined A/D converter is designed and fabricated in 0.18?m CMOS technology.Based on proposed optimization method,some critical analog circuits are redesigned or optimized.The test results show that the optimal design method can effectively improve the performance of A/D converter without increasing additional power consumption or die area.Calibration techniques for pipelined A/D converter have received much attention in the field of analog circuit design in recent years.Background digital calibration in pipelined structure usually contains two types,one is deterministic way and the other is statistical method.A comparison between different pipelined digital calibration method is made,especially in one-order,third-order gain errors and capacitor mismatch errors in MDAC architectures.In deterministic way,the split-ADC architecture is favored as it has fast convergence speed as it split one A/D converter into two-channel sub-ADCs with the same input.However,it dependents on the same input signal,in high speed pipeline application,the clock skew and layout mismatch will seriously affect the performance of split algorithm.In our research,our new approach does not suffer from any time skew drawback and sampling network layout mismatch in split-ADC.And it can be used in high speed pipelined ADC application without strictly clock or sampling network layout matching.Through simulation and analysis,it is proved our new approach has great clock domain mismatch tolerance under high speed condition,and it is suitable for high speed pipelined calibration.In statistical method calibration,it mainly relies on pseudo-random code injection to analog signal path.The convergence times are usually prohibitively long but it hardly adds the burden to analog design and do not need to change too much analog circuits.However,conventional statistical calibration methods have been unable to effectively calibrate capacitor mismatch errors in the MDAC structure with high number of bits.Based on this,this dissertation proposes a mismatch equalization calibration method for high precision MDAC capacitor mismatch,and it is suitable for high precision pipelined A/D converters.Simulation results show that proposed algorithm can effectively improve the dynamic performance of the calibration results,and improve the convergence speed.Finally,the design of a low supply voltage,high speed,high precision,16 bit 100MSPS pipelined A/D converter is proposed.The structure of MDAC,OTA,bootstrapped switch,comparator and other analog unit has been optimized or redesigned to improve the performance.Combined with an improved PN-code injection digital background calibration technique,the gain error,capacitor mismatch and nonlinear errors can be effectively calibrated.Simulation results show that the SFDR and ENOB can be effectively enhanced in our approach.Based on the post-simulation results,it is proved that the design of A/D converter meets the design requirements,and it is suitable for high speed,high precision signal processing,wireless communication and graphics processing system.