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Research And Design Of Low-Voltage Low-Power Pipelined ADC With Advanced Process

Posted on:2011-10-26Degree:DoctorType:Dissertation
Country:ChinaCandidate:M J FanFull Text:PDF
GTID:1118330335992153Subject:Microelectronics and Solid State Electronics
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With the rapid development of the third generation mobile communication network, communication terminal products and consumer electronics products surge in demand, the low-power pipelined ADCs applied in these applications, with 10 to 12 bits and several tens of MHz, have become the international academic and industrial research focus. In general, this type of ADC, as an important mixed-signal module, is embedded in the SOC of the application systems. So this type of ADC needs to be compatible with digital CMOS process and low supply voltage, and lower dissipation. In this dissertation, the pipelined ADC is given with in-depth analysis, and from the low-voltage low-power point of view, the ADC with 12-B and several tens of MHz is given thorough studies at both the system level and circuit level, which includes(1) Two novel low-power low-voltage amplifiers are proposed and designed, which can work at 1.2V or even lower supply voltage. With the same load and dissipation, the novel amplifiers can provide two times GBW compared with the normal two-stage amplifiers by taking use of Class-AB technique in both stage 1 and stage 2, which enhances the slew rate and transconductance, and shorten the signal settling time.(2) A matching network in the sampling front-end is proposed, which can reduce the non-linearity caused by asymmetric signal path in case of no S/H module. A method to generate the timing of the sampling front-end is proposed. The precise front-end timing is realized by adding AND gate to the existing clock structure and inputting twice sampling frequency clock, which can avoid the phenomenon of much long inverter chain, difficulties of controlling the delay time and large clock jitter, caused by the realization with traditional clock circuits.(3) The negative bias temperture instability (NBTI), the well proximity effect (WPE), the shallow trench isolation (STI) stress effect and other non-ideal factors, are introducd, and the impact on the circuits from these effects are also given. According to the SPICE model of these effects, the layout solution for these effects is proposed, which improves the performance of the the design-for-manufacture (DFM) and the back-end simulation results.(4) The improved CMOS switches are proposed in the signal path of the MDAC. With the same voltage (1.2V) and size, the improved CMOS switches are with resistance which is 50% lower than that of the normal CMOS switches.(5) A high-performance low-jitter on-chip clock driver is used. The differential sine waves are required to be put into the chip and shaped by the on-chip pre-amplifying circuits to generate clock, by which the common-mode signal jitter is inhibited, and clock jitter can be reduced to 0.5ps or even lower. The clock jitter can be monitored by the back-end simulation. Based on the above research, two cases of low-voltage low-power ADC design are presented in the thesis. One is a 12-B 40-MS/s pipelined ADC based on SMIC 0.13-um 1.2-V 1P8M mixed signal CMOS process. The measured results show that the pipelined ADC are with 60.5-dB SNDR,60.2-dB SNR,78.2-dB SFDR,-75.5-dB THD,±0.45 LSB DNL,-6~4 LSB INL and 15.6-mW consumption under 1.2-V. the other is a 12-B 50-MS/s pipelined ADC based on SMIC 65-nm 1.2-V 1P7M, low-leakage CMOS process, which has been tapeout. The back-end simulation results show that the pipelined ADC are with 73.4-dB SNDR,74.1-dB SNR,83.2-dBSFDR,11.9-B ENOB and 59-mW dissipation under 1.2V supply voltage.
Keywords/Search Tags:ADC, pipeline, low-power, low-voltage, amplifier-sharing, bootstrapped switch, 65nm, op-amp, sampling front-end, switch-capacitance, comparator, clock jitter
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