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Research On Key Technology Of 12Bit 200Msps Pipelined ADC

Posted on:2019-05-21Degree:MasterType:Thesis
Country:ChinaCandidate:J C ZhangFull Text:PDF
GTID:2428330593451643Subject:Microelectronics and Solid State Electronics
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With the rapid development of digital processing technology,ADCs(Analog-Digital Converter)have been required to present much more excellent performance than ever before.ADCs should have higher conversion rate especially in broadband communications.Taking into the consideration that the pipelined ADC is able to compromise accuracy,speed and power consumption,it is preferred in wireless communications and radar systems.The key circuits of 12 Bit 200Msps pipelined ADC are designed and implemented using SMIC 0.13 um CMOS technology.Firstly,the non-ideal effects of pipelined ADC have been analyzed and applied to the behavioral modeling and simulation by Simulink.The key circuit index such as gain and bandwidth of operational amplifier as well as capacitance are being verified and confirmed based on Simulink simulation.Secondly,key circuit modules are designed precisely,like comparator and MDAC of the first stage,bandgap,bootstrapped switch and etc.To optimize power consumption,SHA-less structure is utilized in the overall architecture.Moreover,halving technique towards input signal is applied in the first stage which can raise SNR of the system by enlarging the swing of input signal,in the other hand it does good to reducing power consumption in smaller reference scale.Pre-amplifier of the comparator adopted in the pipelined ADC can expand the input signal before rail-to-rail output,which reduces the offset and accelerates the comparison.In the meanwhile,the introduction of neutralization method weakens the impact of kick-back noise.The simulation to the entire pipelined ADC is executed with Spectre under the supply voltage of 1.2V using sine wave whose frequency is 17 MHz and 170 MHz.The simulation results have indicated that with the sine wave of 170 MHz and sampling rate of 200 MHz,the pipelined ADC achieves SFDR of 86.6dB,SNR of 71 dB,SNDR of 70.8dB as well as ENOB of 11.5Bit,which meets the requirements of the design.The ADC with input signal of 17 MHz shows better performance.
Keywords/Search Tags:Pipelined ADC, High speed comparator, MDAC, SHA-less, Bootstrapped switch
PDF Full Text Request
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