.1.5 Bit / Stage Pipeline Structure Of The Key Unit Of The A / D Converter Circuit Design

System-on-a-chip(SOC) requires the integration of analog circuits and digital circuits on a single chip.Technology compliable, performance optimized A/D converter(ADC)is an important building block as the bridge of the analog world to the digital section in SOC. It is important and necessary to research ADC with high speed, high resolution ,low power dissipation by adopting standard CMOS process.The pipelined ADC can achieve high speed and high resolution. Furthermore, the number of comparators will be decreased, so the area is decreased. In this design, we introduce the unit circuits of pipelined ADC.The sample and hold circuit is employed by the bottom plate sampling technique, which could not only cancel the charge injection error but also eliminate the effect of clock feed-through. The bootstrapped switch is used to improve the gate overdrive voltage. A type of dynamic voltage comparator is used to improve speed and decrease power. The W/L of operational amplifier is optimized using ac small-signal analysis in frequency domain. At last the best ratio is given. The key cells of ADC have been simulated in UMC 0.18um BSIM3_V3.1 digital CMOS process by HSPICE. By theory analysis and simulation,the dc gain of the amplifier is 72.6dB,the gain-bandwidth is 500MHz,and this architecture can realize 9 stage, 10 bit , 40Msamle/s pipelined A/D converter.