Research And Design Of 12bit 50Msps Pipelined A/D Converter

With the explosive development of communication and digital signal processing technology, has formed gradually take the digital system as the main body pattern. An analog-to-digital converter, as an interface between analog signal and digital signal, especially is demanded in video and wireless communication field. At the same time, pipelined ADC has a good tradeoff between speed and dissipation, so it is widely used. In this thesis, a low power 12bit 50MS/s pipelined ADC is designed in TSMC 3.3V 0.35um CMOS process.The design is based on the analysis in view of each kind of ADC structure, and the chose has been possible to balance the tradeoff among speed, resolution and power. The proposed ADC is composed of 8 stages, each stage is 1.5-bit except for the 4-bit first stage, which can enhance the linearity and the 3-bit FLASH last stage. The result of digital error correction circuit is the 12 digital signals. The sample-and-hold circuit based on the folded cascode and gain enhances operational amplifiers and bootstrapped analog switch to reduce the conducting resistance of NMOS switches and the effect of charge injecting. Full differential dynamic comparator is designed, which can save offset voltage; common-mode feedback circuit and digital error correction circuit are designed.All designed circuits are simulated in Spectre of Cadence, the result of simulation indicates the ADC can achieve 12bit converter precision when the sample rate is 50Msps. The range of differential input signal of ADC is -1V～1V; the ADC consumes about 200mW and the DNL is less than 0.5LSB on a 3.3V supply. The results proved out the research ideas. The method of design has preferable value of theory and application.