Design Of A High-Speed High-Resolution Pipelined Analog-To-Digital Converter

Pipelined Analog-to-Digital Converter (ADC) has wide applications with high-resolution and high-speed characters. Based on the analysis of principles, architectures, errors and techniques to improve resolution and decrease power dissipation, this thesis presents a 1.8V 10-bit 100MHz pipelined ADC.It’s composed of a sample-and-hold circuit, eight stages with 1.5bit per stage, and a 2 bit Flash ADC as last stage. The front-end sample-and-hold circuit uses double-sample technique. Bootstrapped sampling switch is applied and achieves remarkable progress on the resolution and linearity of the system. A single stage folded cascade opamp with gain-boosted has high-speed, high-gain as well as large output swing. The multiplying digital -to-analog converter (MDAC) is designed with correlated double sampling technique to overcome the error due to finite DC gain of operational amplifier. Besides, extremely low temperature coefficient bandgap reference circuit and dynamic comparator with low-kickback noise are presented.The ADC’s design is based on the TSMC 0.18μm, mixed signal 1P6M process, which provides MIM capacitor. With 100MHz sampling frequency, behavioral simulation has been performed at the room temperature and the result shows: it achieves SNDR of 57.16dB@8MHz input and SFDR of 72.1dB @8MHz input; the ENOB is over 8.5-bit within the whole nyquist input frequency; the power consumption is 65.7mW.