Design Of14-bit Pipelined Analog-to-digital Converter

Analog to digital converter (ADC) is very important in all the signal processingsystem, with the progress of process level and the demands of the system on A/Dperformance is ever-increasing, make the further development of Pipelined ADC, whichis well compromised between speed and precision. This paper based on0.5)im standardCMOS process, designs a14-bit IMsps Pipelined ADC, complete the design of theinternal mainly cell circuits and the overall structure.In the selection of the system structure, use12bit1.5bit/stage and combine thefinal stage for the2bit Flash ADC, the odd stage and the even stage alternated workunder the control of two-phase non overlapping clock. Then analysis non ideal factors inorder to find the sources of the system error. At last, the correct circuit is used to removethe redundant bits and get14-bit digital output.In the sub module circuits, design the key unit circuits: Sub-ADC, Sub-DAC,coding circuit with simple logic, S/H circuit for capacitance flip type, MDAC circuitand digital correction circuit. In the specific circuit structure, design a two stage fullydifferential operational amplifier, which has a phase margin of57°and the gain of96dB.Also design a switched capacitor comparator with the conversion level about226.7mV,and a two-phase non overlapping clock, a fast bootstrapped switch.In the overall structure, integrate the mainly units to obtain a14-bit pipelined ADC,simulate the whole ADC by using the Specture tool and indicate that the results meet thesystem requirements, finally this ADC achieves DNL for0.175LSB, INL for1.625LSB,ENOB for13.22bit, SFDR for lOODb and THD for97.5dB from the simulation. Theresults reached the requirement of this design and shows that the model is correct.