Research On Test Data Compression Of SoC Based On LFSR Reseeding

With the rapid development in manufacture technology of very-large-scale integration (VLSI), Circuit design mode has changed from vertical mode to horizontal mode. The core reuse can produce more complicated circuit system, i.e. System-on-a-Chip (SoC). The cycle of circuit design has shorted and the risk has reduced, but the increasing complexity of circuit makes testing challenges come. One of the challenges is test data compression. The research on it has paid more attention by many academies, electronic design automatic companies and integrated circuits manufacturers.Test data compression of SoC is studied in the dissertation, which involves compressing the amount of test data (both stimulus and response). Test stimulus compression is described in three categories of schemes: (1) code-based schemes, (2) linear-decompression-based schemes, (3) broadcast-scan-based schemes. Due to linear feedback shift registers (LFSR) is widely used by industry as a linear decompressor, this thesis is focused on the problem of test data compression based LFSR reseeding.Afterwards several techniques for improving the encoding efficiency of the basic LFSR reseeding method are analyzed. Some have high hardware overhead, and the others need complex computation. Therefore, a new scheme for LFSR reseeding based on syncopation of some test patterns is presented in the dissertation. The research shows that the size of LFSR seed depends on the maximal number of specified bits in test patterns. The more specified bits a test pattern has, the more difficultly it is encoded as LFSR seed. Firstly, test patterns in a test set are reordered according to the number of specified bits they have; and then some patterns are syncopated, which have a lot of specified bits and are encoded hard by LFSR. Thus a new test set is produced and encoded as LFSR seeds. The proposed method increases probability of successful encoding, reduces the size of seeds, and achieves the better compression ratio than similar schemes. It also has very simple decoding circuit which outperforms similar schemes. The decoding circuit only consists of an LFSR and a small sequence machine.