LFSR Reseeding Test Scheme Based On Dividing Some Vectors

As the size and the complexity of systems on a chip continue to grow, test data volume has increased dramatically, and test application time increase. In order to apply the large volume of test data to a chip under test, the automatic test equipment (ATE) requires large memory storage and high bandwidth. Otherwise, there is increasing difficulty in performing at-speed testing due to pin inductance and high tester pin costs.Built-in Self-test (BIST) offers a better alternative than conventional external testing methods. By moving test generation, application and test response into the chip itself, BIST eliminates the need for expensive ATE, reduces the test cost. Due to linear feedback shift registers (LFSR) is widely used by industry as BIST, this thesis is focused on the problem of test data compression based LFSR reseeding.Afterwards several traditional schemes for improving the encoding efficiency of the basic LFSR reseeding method are analyzed. Because the size of LFSR seed depends on the maximal number of specified bits in test patterns, some schemes have high hardware overhead, and the others need complex computation.A scheme for LFSR reseeding by syncopation and combination of test patterns is presented. Some test patterns in a test set which have more specified bits than the number that we chose are divided into blocks, and every block has less specified bits than the number. Some successive blocks which have the less specified bits than the number are combined into one block. A flag bit is added on the tail of every block to express whether the block is combined with the next block. Thus the blocks have narrow variation in their number of specified bits.Because test vectors vary widely in their number of specified bits, and the specified bits in a vector always appear together and form some blocks, a novel scheme for increasing test data compression rate is presented. The odd bits of some vectors which have many specified bits, and the even bits of the vector are separated off. It can reduce S_max of the test set and the variation in number of specified bits of vectors.The proposed methods provide greater test data compression with less hardware overhead compared to the same kind encoding schemes.