Research On Test Data Compression Of SoC Based On State Correlativity And Power Division

With the development of integrated circuit manufacturing craft, the integration of single chip is increasing. Due to integrating various intellectual-property (IP) cores, the function of SoC is developed strongly and test data volume grows quickly. However the storage capacity, frequency and bandwidth of the traditional automatic test equipment (ATE) are limited. This results in longer test time and more high cost in the SoC test. The test data compression is a feasible measure to resolve the problems of SoC test and can be used to decrease the SoC test data volume and test time. The dissertation makes research in test data compression of SoC.After introducing SoC test concepts and analyzing some traditional coding method, a novel scheme of test data compression based on LFSR state correlativity is presented. As the correlativity between current LFSR state and some seed, the proposed scheme controls the bits that need to be changed in the seed loading process by control bits, and makes it unnecessary to load all values of the seed while loading seed to generate test vector. The scheme makes the controls simple and less time to load seeds for test data compression. The results of experiments have proved that this scheme has the advantages of reducing the storage and the time of seed applying.Aiming at a large number of sequential data blocks existing in test set, a new test data compression scheme based on power division is presented. Firstly, the test vector set is divided into a number of data blocks, so that the length of each section is precisely a multiple of a power of two which will be judged later whether it is a sequential data block, if it is, it just uses some certain tag bits to express the length of the sequential data block. On the other hand, the sequences which don't have enough length is made to be non-continuous data block, and not to be encoded, so it can avoid the situation that short run length sequences are replaced by long length code. The rule proposed by the scheme reduces the complexity of encoding which makes use of prefix and tail code separately. The decompression architecture for on-chip pattern is a simple finite-state machine, so the process of encoding and decoding is simple, and the communication protocol is also simple. The experimental results show that the scheme can efficiently compress test data.