Research On LFSR Reseeding Method Based On Test Date Compression Of Partial Compatibility

At present the integrated circuit entered a deep Asian micron time, used the 90nm craft the assembly line already to begin the production, this caused the characteristic size of electronic device more and more slightly, the chip scale more and more largely. The number of gate circuits even surpassed 1000 million be allowed to integrate on a single chip. This opened the broader application way for the system integration, thus causes the current system integration to design into one kind "the fashion". A completely system structure integration in an independent chip, realizes a complete system function, namely System-On-Chip, which is called SoC. If many digital cores are integrated on the chip, then it results in large test data volumes. The increasing complexity of circuit makes testing challenges come. One of the challenges is test data compression.Test data compression method of SoC is studied in the thesis. Firstly, test generation, test type and test of SoC are described in this thesis. Due to linear feedback shift registers (LFSR) is widely used by industry as a linear decompression, this thesis is focused on the problem of test data compression based LFSR reseeding.Afterwards several techniques for improving the encoding efficiency of the basic LFSR reseeding method are analyzed. Some have high hardware overhead, and the others need complex computation. Therefore, a new scheme for LFSR reseeding based on partial consistency is presented in the thesis. The research shows that the size of LFSR seed depends on the maximal number of specified bits in test patterns. The more specified bits a test pattern has, the more difficultly it is encoded as LFSR seed. We consider the partial compatibility between two test vectors to reduce the special bits in the vectors. It can reduce the time used to generate the test vectors by using test per-clock. The proposed method increases probability of successful encoding, reduces the size of seeds, and achieves the better compression ratio than similar schemes. It also has very simple decoding circuit which outperforms similar schemes. The decoding circuit only consists of an LFSR and an X-OR gate circuit. Experimental results demonstrate the advantages of the new partial dynamic LFSR reseeding approach.