The Research Of Test Data Compression Based On Coding And Reseeding Techniques

SOC (System-on-a-Chip) . is the development trend of current international VLSI and is the mainstream of IC development in the new century.SOC has incomparable advantages not only in developing period, but also in the system function and performance. However, with the increase in the number of IP cores integrated, and its function becoming more complex, test data volume and test power consumption for SOC grow quickly, test cost become more expensive. All the cases bring more challenges for the SOC test. The thesis makes research in test data compression of SOC embedded digital cores, and proposes several compression/decompression schemes for different cases, to improve compression ratio, test application time and reduce hardware overhead, power dissipation possibly. The main work of the thesis are showed as following:Describe the related conceptions of SOC test, structure of SOC test and faced challenges of SOC test in detail. Especially, introduce two kinds of main current research methods of test data compression.Analyze each kind of coding method presented in recent years. Then, we propose a new coding strategy called Co-Prefixal Run Length codes (CPRL), to compress test data and reduce test application time availably. During compression, it generates difference vectors from test data and then encoding the vectors with CPRL codes. Its decompression architecture consists of a decoder and a cyclical scan register (CSR). Experimental results for the hard fault set of the ISCAS-89 benchmark circuits show that the proposed method, which is superiority to hybrid coding, is an efficient compression method.First, we introduce the theories of LFSR and phase shifter. Second, we redesign and implemente the scheme of partial reseeding based on words, which are encoded by two kinds of seed called solid seed and empty seed. During the process, phase shifter implementation and linear equations solving are emphatically described. Then we present its decompression architecture, which has low hardware overhead. Finally, Experimental results for the Mintest set of the ISCAS-89benchmark circuits show that the method can efficiently compress test data and is superiority to FDR codes. So it is an available method for SOC test data volume reduction.