Research And Simulation Test Of Data Compression Base On LFSR Reseeding

With super deep sub-micron technology in integrated circuit the widespread use of electronic devices, and promote the size is shrinking, integration has been greatly improved, and the scale of the chip shows Moore's law of growth. Meanwhile ,IP core of multiplexing technique applied to the SoC design, this technique can not only make the development cycle shortens greatly, and the function of the system and also have very good performance improvement. However, due to the integration of IP core increased, thus making the test data quantity and test time consuming rise sharply. If through expanding the automatic test equipment storage area, increase its transmission bandwidth to solve this problem, inevitably leads to test cost increased substantially. Therefore, compression test data become narrow test amount of data access area, reduce test used time and decrease the test cost as one of the most direct and efficient way.In order to reduce test data quantity, the thesis SoC test data compression method for some launched research, in typical compression method deeply on the basis of analyzing and comparing, put forward the part LFSR heavy sow adjoined scheme. LFSR reseeding by linear feedback registers expanded obtain test data, then will test data filling to scan chain.In LFSR heavy planting technology, the tests are concentrated test vector contained indeed positioning maximal number of coding Smax last generated seed length has very big effect. Generally speaking, coding is due to realize in test vector is contained in the number of positioning indeed more responsible. Therefore, in the coding, according to the plan first before handling test set, using testing vector partly compatibility of compression method, making the test centralized contained indeed positioning of the number has decreased, LFSR seed algorithm complexity reduced, and finally generated seed length shortens, thus narrowing the test of storage area used, saving the test cost. Through the clock test, shorten the test vector generation of time. Using this scheme, which not only makes the coding efficiency raised, test vector generation time reduced, and the required access area also has greatly improved. Using ISCAS -89 benchmark circuits, the compression method with other methods contrast. Experimental results clearly shows that the compression method has achieved very good effect. Finally, establish a model, the compression method applied to this model. In the design, using built-in since test method, the various modules by VHDL language description, and in Quartus II environment realize simulation.