Research On Test Data Compression Of SoC Based On Power Division And Block Coding

With the rapid development of Integrated Circuits design and manufacturing level and the improved integration on a single chip, especially appearance of System-on-a-Chip (SoC), more and more Intellectual Property (IP Core) are integrated on the circuit system and the complexity of SoC increased rapidly, which caused increasing test data of the test chip. However, the storage capacity, operating frequency and bandwidth of the traditional automatic test equipment (ATE) are limited, which results greatly increased test difficulty , longer test time, higher test power and unaccepted test costs in SoC test .Test data compression method provides an effective solution to resolve the problems of SoC test and it can be used to decrease the test data, test time and test power. The thesis makes research on test data compression of SoC.This article firstly introduces the basic knowledge of SoC test , and then make a theoretical analysis. Concentration on a large number of consecutive blocks in the test cube, we propose a test data compression method of power law division based on dynamic assignment of don't care bits. The basic idea of this method is that which divides the entire test set into four types according the length of 2 power law, and every block is coded with a code table after its don't care bits are filled. The method can make efficiently use of a number of consecutive data blocks of the test data. And the decompression architecture is simple. Compared with traditional coding methods, the compression rate is further improved.The traditional Linear Feedback Shift Registers (LFSR) reseeding fills the don't bits of the test set randomly, which results in too much transition between adjacent bit in the test vector. This caused excessive test power consumption. This thesis presents a LFSR reseeding test data compression method based on block coding. The don't care bits of the test vectors are filled with adjacent-filling. Then the filled test set is divided to equal length block and then to be coded. After that the seeds set is generated by LFSR reseeding and stored in ATE. Experimental results show that this method can not only effectively increase the data compression rate, but also reduce the shift power consumption during test.