Low-power LFSR Reseeding Test Compression Technology For System On Chip Scan Design

The rapid development of semiconductor process technology has accelerated the entry of integrated circuits into the nano/ultra-sub-micron era.With the emergence of system-on-chip,the scale of the circuit,integration and complexity have increased rapidly.IC design,testing and verification face unprecedented technical challenges and thorny problems,excessive test data,high test power consumption,and long test time have become the focus of research in the test field.Excessive test storage requirements result in high test costs.Excessive test power consumption may cause excessive current or voltage to be generated by the circuit under test,resulting in instantaneous system damage,reduced reliability,and unavoidable yield loss,which seriously affects the production and manufacturing of integrated circuits,and thus delays the development of chips for independent intellectual property rights.The research work in this paper focuses on SoC test generation,data compression and low-power test technology.The specific work is as follows:?1?This paper analyzes the research background of system-on-chip test compression and low-power test technology and its research status at home and abroad,and summarizes the principle of system-on-chip test,test vector generation technology and test data compression method.Introduced system-on-chip built-in test and external low-power test technology.?2?The LFSR reseeding technique can achieve good test compression,but the random filling of the unspecified bits in the test set causes the LFSR reseeding scan test process to generate excessive switching activity,which leads to higher test power consumption.Therefore,this chapter proposes a low-power LFSR reseeding test compression method based on test data block.Through the block encoding process of the test data,and re-sorting and grouping the test vectors that are compatible with the flag bits,at the same time,the specified bits in the test vector are reduced and the test power consumption is reduced.A large number of international standard circuit experiments show that:The method achieves good results in compressing test data?average compression ratio as high as 92.9%?and reducing test power consumption?average power consumption is reduced to 72.4%overall?,and the hardware overhead is within an acceptable range.Since the number of specified bits in different test vectors generated by the ATPG tool is very different,and the LFSR size depends on the test vector with the largest number of specified bits,resulting in an excessively long seed vector,which increases the test storage requirement.Therefore,this chapter proposes a low power dual LFSR reseeding compression method based on vector parity segmentation.The parity vector is processed for the test vector with a larger number of bits,so that the number of specified bits is allocated in the odd/even test vector after slicing,and a new test set is constructed,which effectively reduces theS_max in the test vector,thereby improving the test the compression ratio.Data compression is performed on the new test set using the dual LFSR reseeding method to further reduce the test test power consumption.A large number of international standard circuit experiments show that the method can effectively reduce the power consumption of the system-on-chip test based on the high test compression effect.