Research On Data Compression And Low Power Dissipation Techniques In SoC Test

With the swift development of the system integration and processingtechnology, especially emergence of SoC (System-on-a-chip), IC (IntegratedCircuit) has entered a new period of development. Design of SoC mainly adoptsthe technique of reusable IP (Intellectual-property) cores, and maps the wholesystem to a single chip, so it can greatly short the time to mark, reduce the sizeof products and improve the performance of the system. Therefore, it has beenwidely used in many industrial fields in recent years.With the increase in integration and complexity, the mount of test data andtest power grow rapidly. As poses severe challenges to SoC test, available testresources such as storage capacities and the number of test channels of ATE don’tsatisfy the test requirements, consequently in order to reduce test data and lowertest power, it is necessary for SoC test resources optimization.By studying the relationship between two code words, characteristics ofHuffman coding and scan chain, this paper has launched a study on the above-mentioned key issues.Firstly, according to this feature of many don’t care bits of properlyassignment in the test data, two test data compression schemes based on mixed-compatible data block and complementary compatible data block have beenproposed by exploring the relation of codes after don’t care bits assignment. Thefirst scheme encoding compatible and consecutive data blocks, the later schemeencoding compatible and inversely compatible data blocks. Experimental resultsshow that two schemes can efficient improve compression rate.Secondly, according to Huffman coding characteristic, a test datacompression scheme based on complementary symmetrical Huffman coding hasbeen proposed, this scheme belongs to a statistical coding scheme. Unlike traditional coding based on Huffman coding, which encoding compatible datablocks, this scheme can simultaneously encoding with compatible and inverselycompatible data blocks. Experimental results show that this scheme is superior tosimilar scheme based on Huffman coding.Thirdly, on the basis of an analysis of the causes of test power, two lowpower test schemes are proposed. The scheme based on test vector reordering seepower test as a traveling salesman problem (TSP). Considering ant colonyalgorithm convergence easily to a local optimum, this paper make geneticalgorithm into ant colony algorithm to find the optimal vector ordering; Thescheme based on scan chain modification changes the architecture of the scanchain, which reduces the switching activities so as to reduce test power.Finally, a collaborative optimization scheme of test data compression andtest power based on scan chain adjustment is proposed. In this scheme,compatible scan unit is divided into a group, and the divided scan unit group isreordered, by don’t care bits assignment, test vector reordering and scan slicesdifference, modified test data encoding again so as to reduce test power andimprove compression ratio.