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Research On Scan Test Method Based On MPU Design For Test

Posted on:2021-04-14Degree:MasterType:Thesis
Country:ChinaCandidate:S LiFull Text:PDF
GTID:2518306548982369Subject:IC Engineering
Abstract/Summary:PDF Full Text Request
With the continuous reduction of the integrated circuit process size and the acceleration of industrialization progress,the chip test requirements are becoming higher and higher.Design for Test(DFT)has become an indispensable part of chip design.Scan test is the main implementation method of chip design for test.The research on its design method is very important.When the chip size is very large,test compression is also an important factor to be considered in the scan test.This paper is based on the scan test design of an MPU(Micro Processor Unit)subsystem module.Through the TCU(Test Control Unit)test mode control and DSC(Distributed Slave System Controller)test clock control,ATPG(Automatic Test Patterns Generation)of the subsystem module was realized based on EDT(Embedded Deterministic Test)compression.The test coverage of stuck-at fault and transition fault was 98.15% and 88.37% respectively.The number of test patterns was 5312 and 9054 respectively.The test patterns generated are simulated and optimized.By studying the multi-clock domain scan test clock capture mode,an on-chip clock(OCC)circuit structure for multi-clock domain At-speed test is proposed.The experiment compared LOC(Launch-off-Capture)and LOS(Launch-off-Shift)capture modes.The compression characteristics of EDT structure are studied based on ISCAS'89 benchmark circuits.An optimization method of constant scan channels and constant compression ratio is proposed.The results show that stuck-at fault test data volume is reduced by 3.9-6.4times,and test time is reduced by 3.8-6.2 times,the transition fault test data volume is reduced by 4.0-5.4 times,and the test time is reduced by 3.8-5.2 times.At the same time,the benchmark circuit is designed with EDT bypass and low-power design.The test patterns of bypass mode and low-power mode are generated respectively.This paper has a high reference value for the chip scan test design.The multiclock domain scan test method and clock generation mechanism can be used as the clock scheme of the scan test.The research on the EDT compression characteristics can also be used as the guidelines of scan test compression design.
Keywords/Search Tags:Design for test, Scan test, Micro processor unit, Automatic test pattern generation, Multi-clock domain test, Test compression optimization
PDF Full Text Request
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