Research And Implementation Of Test Data Compression And Lower Power Test Technology Base On Scan Test

With the development of very large scale integration(VLSI) technology, the integration densities and system complexities of VLSI is increasing dramatically, which increase excessively high test cost and test application time. In order to address this problem, advanced test techniques and design for testability(DFT) improving approaches are introduced recently. To perform high-quality VLSI testing, DFT(design for testability) techniques are widely used in IC design nowadays. Along with the DFT techniques developing, test data is becoming huge and test power consumption is increasing. Excessive test data not only need larger test storage, wider bandwidth and longer test time, but also increase test power consumption. While the high test power circuit will cause high IR drop, point overheating, packaging damage and other problems. Therefore, the study of the test data compression methods and low power test techniques is of important practical significance.We deeply analyzed and researched the DFT of the scan-based testing techniques, and summarized the main idea of test technology nowadays. In this paper, we focus on the overlarge test data and high power consumption in IC testing. We propose an optimized X-filling algorithm and a coded-based test data compression algorithm to solve the problem of excessive test data, and a re-design decompressor to cut down the power consumption in testing.The main work of the thesis is as follows :To improve the imperfection of EFDR code’s X-filling method, we proposed an optimized X-filling scheme, which could increase the test data compression ratio and reduce the test application time.we re-designed a simplified EFDR decompressor to reduce its power consumption and hardware overhead. The experimental results based on ISCAS’89 benchmark circuits demonstrate the effectiveness and correctness of the proposed scheme.While too many 01 bits may decrease the test data compression efficiency, we proposed a consecutive-runs and commutative-runs quad-run-length code(CCQR). Experimental results based on ISCAS’89 benchmark circuits show that the proposed algorithm can effectively compress test data and reduce the test application time. Furthermore, the simulation verification results show that the algorithm is effective and correct, and the hardware overhead of decompressor is considerable low.